DS540 Datasheet, PDF (29/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Unexpected Completion
When the slave bridge receives a completion TLP it matches the header Address, Length and Tag to the outstanding
requested Address and Tag. A match failure indicates the TLP is an Unexpected Completion which results in the
completion TLP being discarded and a Slave Unexpected Completion (SUC) interrupt being set. Normal operation
then continues.
Malformed TLP
If a malformed TLP is received, the PCIe hard core identifies the request, then removes it. The Bridge does not see
the TLP.
Abnormal Conditions
This section describes how the Slave side and Master side of the PLBv46 Bridge handle abnormal conditions.
Slave Side Abnormal Conditions
Slave side abnormal conditions are classified into two groups: 1), Bar Length Overrun errors and 2), Completion
TLP Errors. The following sections describe the manner in which the Bridge deals with the error groups.
BAR Length Overrun
The Slave side of the Bridge monitors PLB read and write requests to ensure that the request is within the Base
Address Register (BAR) address range. Any PLB to PCIe read or write request that starts within a valid BAR range
but ends outside the valid BAR range, causes the Bridge to issue a Slave BAR Overrun (SBO) interrupt to the Bridge
Interrupt Status Register. The Bridge also asserts PLB_MRdErr for a read request on the PLB or PLB_MWrErr for a
write request on the PLB.
Completion TLP Errors
Any request to the PCIe bus (except for posted Memory write) requires a completion TLP to complete the associated
PLB request. The Slave side of the PLBv46 Bridge checks the received completion TLPs for errors and checks for
completion TLPs that are never returned (Timeout). Each of the completion TLP error types are discussed in the
subsequent sections. When the Slave side of the PLBv46 Bridge detects completion TLP error (or Timeout), it
discards the erred completion TLP, issues an interrupt to the Bridge Interrupt Status register, automatically reissues
the request to the PCIe bus, then re-arbitrates the PLB. When the Slave side of the PLBv46 Bridge detects two back-
to-back completion TLP errors (or Timeouts), it discards the first erred completion TLP, issues an interrupt to the
Bridge Interrupt Status register, reissues the PCIe TLP request, then re-arbitrates the PLB. When the Slave side
receives the second erred completion TLP (or Timeout), it issues an interrupt to the Bridge Interrupt Status register
and, in the case of a Memory read or I/O read, asserts PLB_MRdErr for the read request on the PLB.
Unsupported Request
A PCIe device may not be capable of satisfying a specific read request. For example, the read request targets an
unsupported PCIe address causing the PCIe completer to return a completion TLP with a completion status of
"0b001 - Unsupported Request". When the slave bridge receives the unsupported request response, it discards the
completion TLP and issues the Slave Unsupported Request (SUR) interrupt to the Bridge Interrupt Status Register.
DS540 June 22, 2011
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Product Specification