DS540 Datasheet, PDF (33/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Link Speed and Compliance
The link speed depends on the C_FAMILY and C_NO_OF_LANES parameters and the PCI Express Base
Specification Compliance is dependent on the C_FAMILY parameter. Table 17 defines the link speed and PCI
Express compliance based on Bridge configuration.
Table 17: Configuration Link Speeds
C_FAMILY C_NO_OF_LANES
Link Speed PCI Express Base Specification Compliance
spartan6
x1
2.5 Gb/s
v1.1
virtex6
x1
2.5 Gb/s
v2.0 ⁽¹⁾
virtex5
x1, x4, x8
2.5 Gb/s
v1.1
1. The Virtex-6 FPGA PCIe is compliant with v2.0 of the PCIe specification, but the bridge does not support 5.0 Gb/s link speed.
Limitations
Slave Bridge Limitations
Burst Size
The slave bridge supports bursts from masters that are smaller than the native size of the bridge. The maximum
burst size supported for a 32-bit master is 64 bytes.
PLB Clock Frequency Range
The bridge has been verified in simulation to work with a PLB clock frequency range of 50 MHz to 150 MHz.
Constraints
The Bridge is asynchronous by design and care must taken to constrain all paths that cross the asynchronous clock
domains. After synthesis has finished, the user must copy the commented “Bridge clock domain crossing
constraints” section from the core level user constraint file and paste this section into the system UCF. The core level
constraint file is located in the bridge instance subdirectory in the EDK project implementation directory. Next, the
user must uncomment the “Bridge clock domain crossing constraints” section and replace the <Add period
constraint here> with the period value used by the MPLB_Clk and SPLB_Clk in the user system.mhs file. After this
is completed the user must run the EDK build bitstream for the new clock domain crossing constraints to be
recognized by the tools.
Example Constraints
Example constraints for the ML505, ML555, ML507 and ML605 boards are provided in the following sections for
reference. The ml505 and ml555 systems are asynchronous designs that use a 125 MHz system clock generated by
a DCM that is connected to the MPLB_Clk and SPLB_Clk inputs to the core. The Bridge_Clk uses a 125 MHz clock
generated from an internal PLL. The ml507 system is an asynchronous design that uses a 100 MHz system clock
generated by a DCM that is connected to the MPLB_Clk and SPLB_Clk inputs to the core. The Bridge_Clk uses a
125 MHz clock generated from an internal PLL. The ml605 system is an asynchronous design that uses a 250 MHz
system clock generated by a DCM that is connected to the MPLB_Clk and SPLB_Clk inputs to the core. The
Bridge_Clk uses a 125 MHz clock generated from an internal PLL.
DS540 June 22, 2011
www.xilinx.com
33
Product Specification