DS540 Datasheet, PDF (23/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 12: Bridge Interrupt Enable Register (Cont’d)
Bit(s)
Name
Core
Access
Reset Value
Description
8
SEP
R/W
Slave Error Poison Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
9
SCA
R/W
Slave Completion Abort Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
10
SBO
R/W
Slave BAR Overrun Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
0b
11
NBE
R/W
Non-Contiguous Byte Enables Enable:
1- Enables Interrupt
0- Disables Interrupt
0b
12
LNKDN
R/W
Link Down Enable:
1- Enables Interrupt
0- Disables Interrupt
13-16
Reserved
0b
17
BME
R/W
Bus Master Enable:
1- Enables Interrupt
0- Disables Interrupt
18-31
Reserved
MSI Address Register (MAR, Offset 0x48)
The MSI Address Register shown in Table 13 provides the address value used to detect an MSI MemWr TLP when
it is received from the PCIe Bus. It is required that a value outside the bar range is written to this register to uniquely
decode a MSI TLP. The register value is compared to the address contained in received MemWr TLPs. When a
matching value is detected, the MSI interrupt is asserted and the data is written to the MDR. Only the 32-bit address
version of MSI is supported. If for some reason a value within the bar range is written to this register, it causes the
MemWr TLP to be treated as both a typical MemWr TLP and a MSI interrupt requesting MemWr TLP, resulting in
spurious MSI interrupt generation.
Table 13: MSI Address Register Bit definitions
Bits
31-0
Name
MSI
Address
Core
Access
R/W
Reset Value
0000_0000h
Description
MSI Address: The 32-bit PCIe address used to compare
with received PCIe address in an MSI MemWr TLP.
DS540 June 22, 2011
www.xilinx.com
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Product Specification