DS540 Datasheet, PDF (20/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 9: PCIe Request Control Register Bit Definitions
Bit(s)
Name
Core
Reset
Access Value
Description
0-20
Reserved
21-23
Max
RO
Payload
Size
000b
MAX PAYLOAD SIZE: This value is set by the RC.
000 = 128
001 = 256
010 = 512
011 = 1024 (Virtex-6 FPGA only)
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
24-28
Reserved
29-31
Max Read RO
Request
Size
010b
MAX READ REQUEST SIZE: This value is set by the RC.
000 = 128
001 = 256
010 = 512
011 = 1024
100 = 2048
101 = 4096
110 = Reserved
111 = Reserved
PCIe Status Register (PSR, Offset 0x3C)
The PCIe Status Register shown in Figure 5 holds the status outputs from the PCIe core. Table 10 provides the bit
description of the PCIe core status outputs. This register is only accessible when LinkUp = 1.
X-Ref Target - Figure 5
Reserved
Link
Width
LU Reserved
0
21 22
25 26 27
31
DS540_05_122309
Figure 5: PCIe Status Register
Table 10: PCIe Status Register Bit Definitions
Bits
Name
Core
Access
Reset Value
0-21
Reserved
22-25
Link Width RO
C_NO_OF_LANES
26
LU
RO
0b
27-31
Reserved
Description
Negotiated Link Width (22 to 25):
0001 = One Lane
0100 = Four Lane (V5 only)
1000 = Eight Lane (V5 only)
Link Up: This bit is set when link training is complete and the
link is operational.
DS540 June 22, 2011
www.xilinx.com
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Product Specification