DS540 Datasheet, PDF (2/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Features (continued)
• Supports one 32-bit or 64-bit PCIe Base Address Register (BAR) memory region mapped to PLB address space
when the Virtex-6 FPGA is configured as Root Complex
• Independent PLB and PCIe clocks
• Supports 32/64-bit PLB version 4.6
• Supports Spartan-6 FPGA x1 PCIe lane configuration at 2.5 GigaTransfers per second (GT/s)
• Supports Virtex-5 FPGA x1, x4, and x8 PCIe lane configuration at 2.5GT/s
• Supports Virtex-6 FPGA x1 PCIe lane configuration at 2.5 GT/s
• Full bridge functionality
• PLB master read and write of a remote PCIe target (both single and burst)
• PCIe requester read and write to a remote PLB slave (both single and multiple)
Functional Description
The PLBv46 Bridge provides transaction level translation of PLB bus commands to PCIe TLP packets and PCIe
requests to PLB bus commands. The architecture of the PLBv46 Bridge is shown in Figure 1. The PLBv46 Bridge is
composed of seven core sections: Slave IPIF, Master IPIF, Management/Register Block, Slave Bridge, Master Bridge,
and Transaction Layer Interface (TLIF) arbiter and the Core Wrapper.
X-Ref Target - Figure 1
PLBv46 Bridge
SPLB
Clock
Bridge
Clock
Core
Wrapper
Management and
Register Interface
PLB PLB
Master
PLB
Slave _PLB
PLB V46
Slave
IPIF
IPIC
PLB Master
Clock
PLB V46
Master
LLink
IPIF
LLINK
CMD
Bus
Slave Bridge
TLP Header Generation,
Address Translation, Range
Check for Segmentation,
Rearbitrate control, Error
Handling
Master Bridge
Header Extraction, Address
Translation, Master CMD
Generation, Error Handling
FIFO
TX
RX
FIFO
TX
RX
MI
MGMT
Interface
PCIe
Hard
Macro
Phy
Interface
Transaction
Layer
Interface
Reset
and
Clocking
BRAM
Buffers
LLink Local Link
Interface
MPLB
Clock
Bridge
Clock
Figure 1: PLBv46 Bridge Architecture
DS540_01_122309
The Slave IPIF provides termination of PLB transactions to the Bridge from a PLB master device such as a Processor.
The Bridge provides a means to translate addresses that are mapped within the PLB address domain to PCIe
domain addresses. Commands from the PLB master are converted into a TLP request and queued in the Slave
Bridge TX FIFO. Packets in this queue are sent to the PCIe core via the TLIF arbiter. The TLIF arbiter round robins
the two TX queues (one for PLB requests and the other for PCIe completions) to determine which one accesses the
single interface on the hard PCIe core.
DS540 June 22, 2011
www.xilinx.com
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Product Specification