DS540 Datasheet, PDF (11/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 2: Parameter Port Dependencies (Cont’d)
Generic Parameter
Affects Depends Description
PCIe Core Configuration Parameters
G49
C_NO_OF_LANES
TXP TXN G1
RXP
RXN
If G1 = spartan6 or virtex6 then
G49 = 1 only
if G1 = virtex5 then
G49 = 1, 4 or 8.
(Note: spartan6 is a fixed x1 lane Endpoint)
G50
C_DEVICE_ID
G51
C_VENDOR_ID
G52
C_CLASS_CODE
G53
C_REV_ID
G54
C_SUBSYSTEM_ID
G3
if G3 = 1 G54 is not meaningful
G55
C_SUBSYSTEM_VENDOR_ID
G3
if G3 = 1 G54 is not meaningful
G56
C_PCIE_CAP_SLOT_IMPLEMENTED
G3
if G3 = 0 G56 is not meaningful
G57
C_REF_CLK_FREQ
G1
if G1 = virtex5, G57 must be = 0
IPIF Parameters
G58
C_MPLB_DWIDTH
G62
G62
G58 must be equal to G62
G59
C_MPLB_AWIDTH
G63
G63
G59 must be equal to G63
G60
C_MPLB_SMALLEST_SLAVE
G61
C_MPLB_NATIVE_DWIDTH
G67
G1, G67 If G1 = spartan6 then
G61 must be set to 32
if G1 = virtex5 or virtex6 then
G61 must be 64 bits wide
G62
C_SPLB_DWIDTH
G63
C_SPLB_AWIDTH
G64
C_SPLB_MID_WIDTH
G65
C_SPLB_NUM_MASTERS
G66
C_SPLB_SMALLEST_MASTER
G67
C_SPLB_NATIVE_DWIDTH
G58
G58
G59
G59
(Note: G61 and G67 must be equal width)
G62 must be equal to G58
G63 must be equal to G59
G61
G1, G61 If G1 = spartan6 then
G67 must be set to 32
if G1 = virtex5 or virtex6 then
G67 must be 64 bits wide
G68
C_BOARD(6)
G69
C_DEVICE(6)
Non-HDL Generics
(Note: G61 and G67 must be equal width)
DS540 June 22, 2011
www.xilinx.com
11
Product Specification