DS540 Datasheet, PDF (3/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
For PLB read requests, the TLP is written into the PLB Bridge TX FIFO and awaits transmission to the PCIe hard
core. After the TLIF arbiter sends this read request to the PCIe core, the TLIF arbiter begins the completion time-out
counter. The Slave Bridge only accepts one PLB read request at a time; however, it can accept as many PLB write
requests as it can fit into the TX FIFO. After the FIFO is full, further PLB commands are re-arbitrated.
The Management/Register Block houses the bulk of the registers used in the bridge. This includes the BARs,
Interrupts, PCIe hard core registers, and miscellaneous status from the PCIe hard core.
The Master Bridge processes read and write command TLPs received from the TLIF and Core Wrapper and creates
the appropriate PLB commands and manages the flow of data associated with each command between the PLB
Master IPIF and the Core Wrapper.
PLBv46 Bridge Parameters
Because many features in the PLBv46 Bridge design can be parameterized, the user can realize a PLB to PCIe bridge
uniquely tailored while using only the resources required for the desired functionality. This approach also achieves
the best possible performance with the lowest resource usage.
The parameters defined for the PLBv46 Bridge are shown in Table 1.
Table 1: Top Level Parameters
Generic Parameter Name
Description
Allowable Values
Default Value VHDL Type
Bridge Parameters
G1
C_FAMILY
Target FPGA Family virtex5, virtex6, spartan6 virtex5
String
G2
C_SUBFAMILY
“lx” - Selects V5LXT
device.
““fx” - Selects
V5FXT device
Note: No effect for
virtex6 and
spartan6.
“LX”, “FX”
“lx”
String
G3
C_INCLUDE_RC
G4
C_BASEADDR
G5
C_HIGHADDR
G6
C_ECAM_BASEADDR
G7
C_ECAM_HIGHADDR
Configures the
0 = Endpoint
0
Bridge to be a Root _{1 = Root Complex}
Complex or an
Endpoint
Device base
address
Valid PLB address ⁽¹⁾⁽³⁾ 0xFFFF_FFFF
Device absolute
high address
Valid PLB address ⁽¹⁾⁽³⁾ 0x0000_0000
ECAM base address Valid PLB address ^(1)(3)(7) 0xFFFF_FFFF
ECAM high address Valid PLB address ^(1)(3)(7) 0x0000_0000
Integer
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
G8
C_COMP_TIMEOUT
Selects the
0 = 50 uS
0
Integer
completion timeout _{1 = 50 mS}
counter value for
PLB to PCIe non-
posted transactions
G9
C_INCLUDE_
Include the registers 0 = exclude
0
BAROFFSET_REG
for high-order bits to _{1 = include}
be substituted in
translation
Integer
DS540 June 22, 2011
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Product Specification