DS540 Datasheet, PDF (39/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
INST "plbv46_pcie_0/*pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst"
LOC = RAMB36_X4Y3;
INST "plbv46_pcie_0/*pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst"
LOC = RAMB36_X4Y2;
INST "plbv46_pcie_0/*pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst"
LOC = RAMB36_X4Y1;
INST "plbv46_pcie_0/*pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst"
LOC = RAMB36_X4Y0;
# Timing critical placements
INST "plbv46_pcie_0/*tx_bridge/vld_q1" LOC = "SLICE_X75Y16";
#################################################################################
## Bridge clock domain crossing constraints
#################################################################################
NET "plbv46_pcie_0/*MPLB_Clk" PERIOD = 10 ns;
NET "plbv46_pcie_0/*SPLB_Clk" PERIOD = 10 ns;
NET "plbv46_pcie_0/*SPLB_Clk" TNM_NET = "SPLB_Clk";
NET "plbv46_pcie_0/*Bridge_Clk" TNM_NET = "Bridge_Clk";
# Timing constraints between clock-domain boundaries
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 10 ns datapathonly;
ML605 Constraints
###############################################################################
# System level pin location constraints
###############################################################################
Net fpga_0_clk_1_sys_clk_p_pin LOC = J9;
Net fpga_0_clk_1_sys_clk_p_pin IOSTANDARD = LVDS_25;
Net fpga_0_clk_1_sys_clk_p_pin DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = H9;
Net fpga_0_clk_1_sys_clk_n_pin IOSTANDARD = LVDS_25;
Net fpga_0_clk_1_sys_clk_n_pin DIFF_TERM = TRUE;
Net fpga_0_rst_1_sys_rst_pin LOC = H10;
Net fpga_0_rst_1_sys_rst_pin IOSTANDARD = SSTL15;
Net fpga_0_rst_1_sys_rst_pin PULLUP;
DS540 June 22, 2011
www.xilinx.com
39
Product Specification