DS540 Datasheet, PDF (19/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
PCIe Requester ID Register (PRIDR, Offset 0x34)
The PCIe Requester ID Register shown in Figure 3 provides the Bus Number, Device Number and Function
Number of the Bridge. When the bridge is configured as a Root Complex (C_INCLUDE_RC = 1), the Bus Number
and Device Number values are writable. This register provides the Requester ID for all TLPs generated by the slave
bridge, including the Power Limit Message, which is automatically sent, after link up, when the BME bit is set in the
Bridge Control Register (BCR). Therefore, the self-configuration SW must set the PRIDR register before setting the
BME bit, or the Power Limit Message may be sent with the wrong requester ID. When the bridge is configured as
an Endpoint (C_INCLUDE_RC = 0), the register is read only and is only valid when LinkUp = 1.
X-Ref Target - Figure 3
Reserved
Bus Number
Device No. Function
0
15 16
23 24
28 29 31
DS540_03_122309
Figure 3: PCIe Requester ID Register
Table 8: PCIe Requester ID Register Bit Definitions
Bit(s)
Name
Core
Reset
Access Value
Description
0-15
Not Used
16-23
Bus
Number
RO for
00h
Endpoint,
R/W for
Root
Complex
Bus Number: When configured as an Endpoint (C_INCLUDE_RC = 0),
this is the bus number of the Bridge assigned by the Root Complex upon
enumeration. When configured as a Root Complex (C_INCLUDE_RC =
1), this is where the bus number of the Bridge must be written by the
user.
24-28
Device
Number
RO for
0h
Endpoint,
R/W for
Root
Complex
Device Number: When configured as an Endpoint (C_INCLUDE_RC =
0), this is the device number of the Bridge assigned by the Root Complex
upon enumeration. When configured as a Root Complex
(C_INCLUDE_RC = 1), this is where the device number of the Bridge
must be written by the user.
29-31
Function RO
Number
000b
Function Number: This is the function number of the Bridge. This value
is hard coded to “000” inside the Bridge.
PCIe Request Control Register (PRCR, Offset 0x38)
The PCIe Requester Control Register shown in Figure 4 shows the max payload size and max read request size
status from the hard block. PLBv46 Bridge limits the max payload size to 1024 bytes for Virtex-6 FPGAs and 512
bytes for Virtex-5 and Spartan-6 FPGAs, when performing PLB to PCIe memory transactions. The maximum read
request size is 4096 bytes when performing PCIe to PLB memory read requests. The data in this register is only valid
when LinkUp = 1.
X-Ref Target - Figure 4
Reserved
MAX_READ_REQUEST_SIZE
Reserved
0
20 21 23 24
28 29 31
MAX_PAYLOAD_SIZE
Figure 4: PCIe Request Control Register
DS540_04_122309
DS540 June 22, 2011
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19
Product Specification