DS540 Datasheet, PDF (44/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Acronym
MUR
PLB
PLL
PRCR
PRIDR
PSR
R
RAM
RC
RO
SBO
SCA
SCT
SEP
SPLB
SW
TLIF
TLP
UCF
UR
VHDL
XPS
XST
Spelled Out
Master Unsupported Request
Processor Local Bus
Phase-Locked Loop
PCIe Requester Control Register
PCIe Requester ID Register
PCIe Status Register
Read
Random Access Memory
Root Complex
Read Only
Slave BAR Overrun
Slave Completer Abort
Slave Completion Timeout
Slave Error Poison
Slave PLB
Software
Transaction Layer Interface
Transaction Layer Packets
User Constraints File
Unsupported Request
VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits)
Xilinx Platform Studio
Xilinx Synthesis Technology
DS540 June 22, 2011
www.xilinx.com
44
Product Specification