DS540 Datasheet, PDF (18/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Bridge Control Register (BCR, Offset 0x30)
The Bridge Control Register shown in Figure 2 enables the operation of the slave bridge and master bridge via the
Bridge Control Register bits BME, E0-E2.
X-Ref Target - Figure 2
PLBv46 Bridge
SPLB
Clock
Bridge
Clock
Core
Wrapper
Management and
Register Interface
PLB PLB
Master
PLB
Slave _PLB
PLB V46
Slave IPIC
PLB Master
Clock
PLB V46
Master
LLink
LLINK
CMD
Bus
Slave Bridge
TLP Header Generation,
Address Translation, Range
Check for Segmentation,
Rearbitrate control, Error
Handling
FIFO36-
Based
FIFO
TX
RX
Master Bridge
Header Extraction, Address
Translation, Master CMD
Generation, Error Handling
FIFO36-
Based
FIFO
TX
RX
MI
MGMT
Interface
PCIe
Hard
Macro
Phy
Interface
Transaction
Layer
Interface
Reset
and
Clocking
BRAM
Buffers
LLink Local Link
Interface
MPLB
Clock
Bridge
Clock
Figure 2: Bridge Control Register
DS540_01_122309
Table 7: Bridge Control Register Bit Definitions
Bit(s)
Name
Core
Reset
Access Value
Description
0-22
Reserved
23
BME
R/W
0b
Bus Master Enable: This is used to enable the PCIe bus master
capability and completion capability. This prevents both the requests from
being sourced by the PCIe hard core and the PLB slave read completions
from being returned to a PCIe requester if set to 0. PLB master requests
are re-arbitrated on the PLB when set to 0. The Bus Maser Enable bit of
the PCI Configuration space also stops the PLB slave read completions
from being returned to a PCIe requester if set to 0.
24-28
Reserved
29-31
E0, E1, E2 R/W
000000b
Enable PCIe BAR 0-2: This is used to enable the PCIe BARs after SW
configuration. This allows proper TLP address filtering and translation to
occur. Active high.
Bit 31- BAR0 enable
Bit 30- BAR1 enable
Bit 29- BAR2 enable
DS540 June 22, 2011
www.xilinx.com
18
Product Specification