DS540 Datasheet, PDF (40/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Net fpga_0_rst_1_sys_rst_pin TIG;
###############################################################################
# System level clock constraints
###############################################################################
NET "PCIe_Bridge/REFCLK" TNM_NET = "PCIe_RefClk" ;
NET "*/pcie_clocking_i/clk_125" TNM_NET = "PCIe_CLK_125" ;
TIMESPEC "TS_PCIe_RefClk" = PERIOD "PCIe_RefClk" 250.00 MHz HIGH 50 % ;
TIMESPEC "TS_PCIe_CLK_125" = PERIOD "PCIe_CLK_125" TS_PCIe_RefClk/2.0 HIGH 50 % PRIORITY 100;
###############################################################################
###### PCIe_Bridge constraints
###############################################################################
# SYS clock 250 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-6 FPGA serial transceiver
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each serial transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# See the Virtex-5 FPGA GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
INST "*/PCIe_Diff_Clk/USE_IBUFDS_GTXE1.GEN_IBUFDS_GTXE1[0].IBUFDS_GTXE1_I" LOC =
IBUFDS_GTXE1_X0Y4;
# Transceiver instance placement. This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs. See the # Virtex-6 FPGA GT Transceiver User Guide (UG) for more
# information.
# PCIe Lane 0
INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used. #
INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;
################################################################################
# Bridge clock domain crossing constraints
################################################################################
NET "plbv46_pcie_0/*SPLB_Clk"
TNM_NET = "SPLB_Clk";
DS540 June 22, 2011
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Product Specification