DS540 Datasheet, PDF (5/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 1: Top Level Parameters (Cont’d)
Generic Parameter Name
G25
C_IPIFBAR2PCIBAR_2
Description
PCI BAR to which
PLB BAR_2 is
mapped
Allowable Values
Valid PCIe address ⁽²⁾
Default Value VHDL Type
0xFFFF_FFFF std_logic_vector
G26
C_IPIFBAR_3
PLB BAR_3
aperture low
address
G27
C_IPIFBAR_HIGHADDR_3
PLB BAR_3
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address ^(1)(3)(4) 0x0000_0000 std_logic_vector
G28
C_IPIFBAR_AS_3
PLB BAR_3 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G29
C_IPIFBAR_
SPACE_TYPE_3
G30
C_IPIFBAR2PCIBAR_3
PLB BAR 3 Type
PCI BAR to which
PLB BAR_3 is
mapped
0 = I/O space
1 = Memory space
Valid PCIe address ⁽²⁾
1
Integer
0xFFFF_FFFF std_logic_vector
G31
C_IPIFBAR_4
PLB BAR_4
aperture low
address
G32
C_IPIFBAR_HIGHADDR_4
PLB BAR_4
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address^(1)(3)(4) 0x0000_0000 std_logic_vector
G33
C_IPIFBAR_AS_4
PLB BAR_4 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G34
C_IPIFBAR_SPACE_TYPE_4 PLB BAR 4 Type 0 = I/O space
1
1 = Memory space
Integer
G35
C_IPIFBAR2PCIBAR_4
PCI BAR to which
PLB BAR_4 is
mapped
Valid PCIe address ⁽²⁾
0xFFFF_FFFF std_logic_vector
G36
C_IPIFBAR_5
PLB BAR_5
aperture low
address
G37
C_IPIFBAR_HIGHADDR_5
PLB BAR_5
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address ^(1)(3)(4) 0x0000_0000 std_logic_vector
G38
C_IPIFBAR_AS_5
PLB BAR_5 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G39
C_IPIFBAR_SPACE_TYPE_5 PLB BAR 5 Type 0 = I/O space
1
1 = Memory space
Integer
G40
C_IPIFBAR2PCIBAR_5
PCI BAR to which
PLB BAR_5 is
mapped
Valid PCIe address ⁽²⁾
0xFFFF_FFFF std_logic_vector
G41
C_PCIBAR_NUM
Number of PCI
1- 3;
3
address apertures
that can be
accessed
1 = BAR_0 enabled
2 = BAR_0, BAR_1
enabled
3 = BAR_0, BAR_1,
BAR_2 enabled
Integer
DS540 June 22, 2011
www.xilinx.com
5
Product Specification