DS540 Datasheet, PDF (37/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
INST "plbv46_pcie_0/*pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst"
LOC = RAMB36_X1Y9;
INST "plbv46_pcie_0/*pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst"
LOC = RAMB36_X1Y8;
INST "plbv46_pcie_0/*pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst"
LOC = RAMB36_X1Y7;
INST "plbv46_pcie_0/*pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst"
LOC = RAMB36_X1Y6;
INST "plbv46_pcie_0/*pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"
LOC = RAMB36_X1Y5;
# Timing critical placements
INST "plbv46_pcie_0/*tx_bridge/shift_pipe1” LOC = "SLICE_X59Y36";
INST "plbv46_pcie_0/*arb_inst/completion_available" LOC = "SLICE_X58Y26";
INST "plbv46_pcie_0/*management_interface/mgmt_rdata_d1_3” LOC = "SLICE_X59Y25";
################################################################################
# Bridge clock domain crossing constraints
################################################################################
NET "plbv46_pcie_0/*SPLB_Clk"
TNM_NET = "SPLB_Clk";
NET "plbv46_pcie_0/*Bridge_Clk"
TNM_NET = "Bridge_Clk";
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 10 ns datapathonly;
ML507 Constraints
###############################################################################
# System level pin location constraints
###############################################################################
Net system_clk_pin LOC=AH15;# X1 = 100MHz
Net system_clk_pin IOSTANDARD = LVCMOS33;
Net system_reset_pin LOC=E9;
Net system_reset_pin IOSTANDARD=LVCMOS33;
Net perstn_pin LOC=W10;
Net perstn_pin IOSTANDARD=LVCMOS33;
Net ref_clk_p_pin<0> LOC=AF4;
Net ref_clk_n_pin<0> LOC=AF3;
DS540 June 22, 2011
www.xilinx.com
37
Product Specification