DS540 Datasheet, PDF (13/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 3: Top Level Interface Signals (Cont’d)
Signal Name
I/O
Description
Sl_wrDAck
O
Slave write data acknowledge
Sl_wrComp
O
Slave write transfer complete indicator
Sl_wrBTerm
O
Slave terminate write burst transfer
Sl_rdDBus(0:C_SPLB_DWIDTH-1)
O
Slave read data bus
Sl_rdWdAddr(0:3)
O
Slave read word address
Sl_rdDAck
O
Slave read data acknowledge
Sl_rdComp
O
Slave read transfer complete indicator
Sl_rdBTerm
O
Slave terminate read burst transfer
Sl_MBusy(0:C_SPLB_NUM_MASTERS-1)
O
Slave busy indicator
Sl_MRdErr(0:C_SPLB_NUM_MASTERS-1)
O
Slave read error indicator
Sl_MWrErr(0:C_SPLB_NUM_MASTERS-1)
O
Slave write error indicator
Sl_MIRQ(0:C_SPLB_NUM_MASTERS-1)
O
Slave Interrupt
MPLB_Clk
PLB Master Interface
I
Master PLB Clock ⁽¹⁾
MPLB_Rst
I
Master PLB Reset
PLB_MAddrAck
I
PLB Master address acknowledge
PLB_MBusy
I
PLB Master slave busy indicator
PLB_MRdErr
I
PLB Master slave read error indicator
PLB_MWrErr
I
PLB Master slave write error indicator
PLB_MRdBTerm
I
PLB Master terminate read burst indicator
PLB_MRdDAck
I
PLB Master read data acknowledge
PLB_MRdDBus [0:C_MPLB_DWIDTH -1]
I
PLB Master read data bus
PLB_MRdWdAddr [0:3]
I
PLB Master read word address
PLB_MRearbitrate
I
PLB Master bus rearbitrate indicator
PLB_MSSize [0:1]
I
PLB Master slave data bus port width
PLB_MWrBTerm
I
PLB Master terminate write burst indicator
PLB_MWrDAck
I
PLB Master write data acknowledge
PLB_MTimeout
I
PLB Address Timeout
PLB_MIRQ
I
PLB interrupt
M_abort
O
Master abort bus request indicator
M_ABus[0:C_MPLB_AWIDTH-1]
O
Master address bus
M_BE[0:C_MPLB_DWIDTH/8-1]
O
Master byte enables
M_busLock
O
Master bus lock
M_MSize[0:1]
O
Master data bus port width
M_priority
O
Master bus request priority
M_rdBurst
O
Master burst read transfer indicator
DS540 June 22, 2011
www.xilinx.com
13
Product Specification