DS540 Datasheet, PDF (15/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Memory Map
The memory map shown in Table 4 shows the address mapping for the PLBv46 Bridge. These registers are
described in more detail in the following sections. All registers are offset from C_BASEADDR.
During a reset (either from the bus or from the IPIF register RESETMODULEREG) all registers are reset to their
default values. The PCIe hard core registers are described in LogiCORE IP Endpoint Block Plus v1.13 for PCI Express
User Guide (UG341), LogiCORE IP Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express User Guide (UG654)
and LogiCORE IP Virtex-6 FPGA Integrated Block v1.4 for PCI Express User Guide (UG517).
Table 4: Memory Map
R/W Offset
R/W 0x0000
R/W 0x0004
R/W 0x0008
R/W 0x000C
R/W 0x0010
R/W 0x0014
R/W 0x0018
R/W 0x001C
R/W 0x0020
R/W 0x0024
R/W 0x0028
R/W 0x002C
Upper Address
Lower Address
Upper Address
Lower Address
Upper Address
Lower Address
Upper Address
Lower Address
Upper Address
Lower Address
Upper Address
Lower Address
Register
Mnemonic
IPIFBAR2PCIBAR_0U
IPIFBAR2PCIBAR_0L
IPIFBAR2PCIBAR_1U
IPIFBAR2PCIBAR_1L
IPIFBAR2PCIBAR_2U
IPIFBAR2PCIBAR_2L
IPIFBAR2PCIBAR_3U
IPIFBAR2PCIBAR_3L
IPIFBAR2PCIBAR_4U
IPIFBAR2PCIBAR_4L
IPIFBAR2PCIBAR_5U
IPIFBAR2PCIBAR_5L
R/W 0x0030
Reserved
Reserved
BCR
R/W-
RC, 0x0034
RO-EP
RO 0x0038
RO 0x003C
Reserved
Reserved
Reserved
Bus Number
Device No. Function
Max
Payload
Size
Reserved
Max
Read
Request
Size
Link Width
Reserved
PRIDR
PRCR
PSR
R/TOW 0x0040
Reserved
Reserved
BIR
R/W 0x0044
Reserved
Reserved
R/W 0x0048
MSI Address
RO 0x004C
MSI Data
0x0050
-
0x1FE
C
Reserved
PCIe Core Management Interface Registers
R/W-
RC,
RO-EP
0x2000
-
0x3FF
C
See UG341 LogiCORE IP Endpoint Block Plus for PCIe Users Guide, UG654 LogiCORE IP Spartan-6 FPGA
Integrated Endpoint Block for PCI Express User Guide and UG517 LogiCORE IP Virtex-6 FPGA Integrated
Block for PCI Express User Guide, in the "PCIe Configuration Space Header" table for a detailed description of
these registers. To calculate the PLB address offset for a particular register, add 0x2000 to the register address.
Offset
BIER
MAR
MDR
Reserved
PCIeCore
Registers
Register
Mnemonic
DS540 June 22, 2011
www.xilinx.com
15
Product Specification