DS540 Datasheet, PDF (4/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 1: Top Level Parameters (Cont’d)
Generic Parameter Name
Description
Allowable Values
Default Value VHDL Type
G10
C_IPIFBAR_NUM
Number of PLB
address apertures
that can be
accessed
1- 6;
6
1 = BAR_0 enabled
2 = BAR_0, BAR_1
enabled
3 = BAR_0, BAR_1,
BAR_2 enabled
4 = BAR_0, BAR_1,
BAR2, BAR_3 enabled
5 = BAR_0, BAR_1,
BAR_2, BAR_3, BAR_4
enabled
6 = BAR_0 through
BAR_5 enabled
Integer
G11
C_IPIFBAR_0
PLB BAR_0
aperture low
address
G12
C_IPIFBAR_HIGHADDR_0
PLB BAR_0
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address ^(1)(3)(4) 0x0000_0000 std_logic_vector
G13
C_IPIFBAR_AS_0
PLB BAR_0 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G14
C_IPIFBAR_SPACE_TYPE_0 PLB BAR 0 Type 0 = I/O space
1
1 = Memory space
Integer
G15
C_IPIFBAR2PCIBAR_0
PCI BAR to which
PLB BAR_0 is
mapped
Valid PCIe address ⁽²⁾
0xFFFF_FFFF std_logic_vector
G16
C_IPIFBAR_1
PLB BAR_1
aperture low
address
G17
C_IPIFBAR_HIGHADDR_1
PLB BAR_1
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address ^(1)(3)(4) 0x0000_0000 std_logic_vector
G18
C_IPIFBAR_AS_1
PLB BAR_1 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G19
C_IPIFBAR_SPACE_TYPE_1 PLB BAR 1Type
0 = I/O space
1
1 = Memory space
Integer
G20
C_IPIFBAR2PCIBAR_1
PCI BAR to which
PLB BAR_1 is
mapped
Valid PCIe address ⁽²⁾
0xFFFF_FFFF std_logic_vector
G21
C_IPIFBAR_2
PLB BAR_2
aperture low
address
G22
C_IPIFBAR_HIGHADDR_2
PLB BAR_2
aperture high
address
Valid PLB address
(1)(3)(4)(5)
0xFFFF_FFFF std_logic_vector
Valid PLB address ^(1)(3)(4) 0x0000_0000 std_logic_vector
G23
C_IPIFBAR_AS_2
PLB BAR_2 address 0 = 32 bits
0
Integer
size
1 = 64 bits
G24
C_IPIFBAR_SPACE_TYPE_2 PLB BAR 2 Type 0 = I/O space
1
1 = Memory space
Integer
DS540 June 22, 2011
www.xilinx.com
4
Product Specification