DS540 Datasheet, PDF (42/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Resource Utilization
The PLBv46 Bridge core resources used in the Virtex-5, Virtex-6, or Spartan-6 FPGAs are detailed in Table 19.
Table 19: PLBv46 Bridge Core Resources Used
Device Family
Resource
Slice LUT
Virtex-5
Slice Register
BRAM36
BRAM18
Slice LUT
Virtex -6
Slice Register
BRAM36
BRAM18
Slice LUT
Spartan-6
Slice Register
BRAM16
BRAM8
1. 6 IPIFBAR (64-bit), 3 PCIBAR (64-bit) and x8 lane width
2. 1 IPIFBAR (32-bit), 1 PCIBAR (64-bit) and x1 lane width
3. 6 IPIFBAR (32-bit), 3 PCIBAR (64-bit) and x1 lane width
Max
8231⁽¹⁾
7497⁽¹⁾
10⁽¹⁾
6⁽¹⁾
3762⁽³⁾
2505⁽³⁾
6⁽³⁾
2⁽³⁾
2868⁽³⁾
2208⁽³⁾
9⁽³⁾
2⁽³⁾
Min
7833⁽²⁾
6871⁽²⁾
10⁽²⁾
6 ⁽²⁾
3330⁽²⁾
2130⁽²⁾
6⁽²⁾
2⁽²⁾
2658⁽²⁾
1833⁽²⁾
9⁽²⁾
2⁽²⁾
Specification Exceptions
N/A
Reference Documents
To search for documentation, see the Documentation page on the Xilinx website.
1. LogiCORE IP Endpoint Block Plus v1.13 for PCI Express User Guide (UG341)
2. LogiCORE IP Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express User Guide (UG654)
3. LogiCORE IP Virtex-6 FPGA Integrated Block v1.4 for PCI Express User Guide (UG517)
4. PLBV46 Master (DS566)
5. PCI Express Base Specification Revision 2.1
Support
Xilinx provides technical support for this LogiCORE™ IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
DS540 June 22, 2011
www.xilinx.com
42
Product Specification