DS540 Datasheet, PDF (28/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Example 4
This example shows the generic settings to set up a combination of 2 independent 32-bit IPIF BARs and 2
independent 64-bit BARs and address translation of PLB addresses to a remote PCIe address space. This setting of
IPIF BARs does not depend on the PCIe BARs within the Bridge.
In this example, where C_IPIFBAR_NUM=4, the following assignments for each range are made:
C_IPIFBAR_AS_0=0
C_IPIFBAR_0=0x12340000
C_IPIF_HIGHADDR_0=0x1234FFFF
C_IPIFBAR2PCIBAR_0=0x5671XXXX (Bits 16-31 are don’t cares)
C_IPIFBAR_AS_1=1
C_IPIFBAR_1=0xABCDE000
C_IPIF_HIGHADDR_1=0xABCDFFFF
C_IPIFBAR2PCIBAR_1=0x50000000FEDC0XXX (Bits 51-63 are don’t cares)
C_IPIFBAR_AS_2=0
C_IPIFBAR_2=0xFE000000
C_IPIF_HIGHADDR_2=0xFFFFFFFF
C_IPIFBAR2PCIBAR_2=0x40XXXXXX (Bits 7-31 are don’t cares)
C_IPIFBAR_AS_3=1
C_IPIFBAR_3=0x00000000
C_IPIF_HIGHADDR_3=0x0000007F
C_IPIFBAR2PCIBAR_3=0x600000008765438X (Bits 57-63 are don’t cares)
Accessing the Bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus yields 0x56710ABC on the PCIe bus.
Accessing the Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields 0x50000000FEDC1123 on the
PCIe bus.
Accessing the Bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus yields 0x41FEDCBA on the PCIe bus.
Accessing the PLBv46 Bridge IPIFBAR_3 with address 0x00000071 on the PLB bus yields
0x60000000876543F1 on the PCIe bus.
Interrupts
The Bridge has two interrupt mechanisms to prompt devices external to the Bridge of certain events. The first is the
IP2INTC_Irpt interrupt pin and the second is the MSI_REQUEST pin.
The IP2INTC_Irpt pin can be configured to send interrupts based on the settings of the Bridge Interrupt Enable
register. The IP2INTC_Irpt signals interrupts to devices attached to the PLB side of the Bridge. One of the interrupts
defined in the Bridge Interrupt Enable register is used to indicate the receipt of a Message Signaled Interrupt when
the bridge is operating in Root Complex mode (C_INCLUDE_RC=1).
The MSI_REQUEST pin is used to trigger a Message Signaled Interrupt via a special MemWr TLP to an external
PCIe Root Complex on the PCIe side of the Bridge. The MSI_REQUEST pin input is level detected and the pin must
see a level high (level = 1) for a minimum of two PLB_Clks before the Bridge sends the Message Signaled Interrupt.
The address and data contained in this MemWr TLP are determined by configuration of registers within the PCIe
hard block by an external PCIe Root Complex. This MSI_REQUEST pin input is valid only when the bridge is
operating in Endpoint mode (C_INCLUDE_RC=0).
DS540 June 22, 2011
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