DS540 Datasheet, PDF (12/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Top-level Interface Signals
The interface signals for the PLBv46 Bridge are described in Table 3. While there are independent clocks for the
SPLB and MPLB interfaces these clocks are required to be synchronous and of the same frequency.
Table 3: Top Level Interface Signals
Signal Name
IP2INTC_Irpt
SPLB_Clk
SPLB_Rst
PLB_ABus [0:C_SPLB_AWIDTH-1]
PLB_PAValid
PLB_masterID [0:C_SPLB_MID_WIDTH-1]
PLB_abort
PLB_RNW
PLB_BE [0:(C_SPLB_DWIDTH/8)-1]
PLB_MSize [0:1]
PLB_size [0:3]
PLB_type [0:2]
PLB_wrDBus [0:C_SPLB_DWIDTH-1]
PLB_wrBurst
PLB_rdBurst
PLB_SAValid
PLB_UABus[0:31]
PLB_BusLock
PLB_LockErr
PLB_TAttribute[0:15]
PLB_RdPrim
PLB_WrPrim
PLB_RDPendPri[0:1]
PLB_WrPendPri[0:1]
PLB_RdPendReq
PLB_WrPendReq
Sl_addAck
Sl_SSize(0:1)
Sl_wait
Sl_rearbitrate
I/O
Description
Global Signals
O
Interrupt signal
PLB Slave Interface
I
Slave PLB Clock ⁽¹⁾
I
Slave PLB Reset
I
PLB address bus
I
PLB primary address valid indicator
I
PLB current master identifier
I
PLB abort bus request indicator
I
PLB read not write
I
PLB byte enables
I
PLB master data bus size
I
PLB transfer size
I
PLB transfer type
I
PLB write data bus
I
PLB burst write transfer indicator
I
PLB burst read transfer indicator
I
PLB Secondary address valid
I
PLB Upper address bus
I
PLB Bus Lock
I
PLB Lock Error
I
PLB Attribute
I
PLB Read Primary
I
PLB Write Primary
I
PLB Read Pending on Primary
I
PLB Write Pending on Primary
I
PLB Read Pending Request
I
PLB Write Pending Request
O
Slave address acknowledge
O
Slave data bus size
O
Slave wait indicator
O
Slave rearbitrate bus indicator
DS540 June 22, 2011
www.xilinx.com
12
Product Specification