DS540 Datasheet, PDF (26/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Address Translation
PCIe address space is different than PLB address space and to access one address space from another address space
requires an address translation process.
The PLB side the bridge supports up to six 32-bit or 64-bit IPIF base address registers (BARs) and the generics used
to configure the BARs are C_IPIFBAR_NUM, C_IPIFBAR_n, C_IPIFBAR_HIGHADDR_n, C_IPIFBAR2PCIBAR_n
and C_IPIFBAR_AS_n, where "n" represents a particular IPIF BAR number from 0 to 5. The PCIe side the bridge
supports up to three 64-bit PCI™ BARs and the generics used to configure the BARs are C_PCIBAR_NUM,
C_PCI2IPIFBAR_n and C_PCIBAR_LEN_n, where "n" represents a particular PCIe BAR number from 0 to 2. The
C_INCLUDE_BAROFFSET_REG generic allows for dynamic address translation. When this parameter is set to one,
the IPIFBAR2PCIBAR_n translation vectors can be changed via software.
In the 4 examples to follow, Example 1 demonstrates how to set up four 32-bit IPIF BARs and translate the PLB
address to a PCIe address. Example 2 demonstrates how to set up three 64-bit IPIF BARs and translate the PLB
address to a PCIe address. Example 3 demonstrates how to set up two 64-bit PCIe BARs and translate the PCI
address to a PLB address. Example 4 demonstrates how set up a combination of two 32-bit IPIF BARs and two 64-
bit IPIF BARs and translate the PLB address to PCIe address.
Example 1
This example shows the generic settings to set up 4 independent 32-bit IPIF BARs and address translation of PLB
addresses to a remote PCIe address space. This setting of IPIF BARs does not depend on the PCIe BARs within the
Bridge.
In this example, where C_IPIFBAR_NUM=4, the following assignments for each range are made:
C_IPIFBAR_AS_0=0
C_IPIFBAR_0=0x12340000
C_IPIF_HIGHADDR_0=0x1234FFFF
C_IPIFBAR2PCIBAR_0=0x5671XXXX (Bits 16-31 are don’t cares)
C_IPIFBAR_AS_1=0
C_IPIFBAR_1=0xABCDE000
C_IPIF_HIGHADDR_1=0xABCDFFFF
C_IPIFBAR2PCIBAR_1=0xFEDC0XXX (Bits 19-31 are don’t cares)
C_IPIFBAR_AS_2=0
C_IPIFBAR_2=0xFE000000
C_IPIF_HIGHADDR_2=0xFFFFFFFF
C_IPIFBAR2PCIBAR_2=0x40XXXXXX (Bits 7-31 are don’t cares)
C_IPIFBAR_AS_3=0
C_IPIFBAR_3=0x00000000
C_IPIF_HIGHADDR_3=0x0000007F
C_IPIFBAR2PCIBAR_3=0x8765438X (Bits 25-31 are don’t cares)
Accessing the Bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus yields 0x56710ABC on the PCIe bus.
Accessing the Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields 0xFEDC1123 on the PCIe bus.
Accessing the Bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus yields 0x41FEDCBA on the PCIe bus.
Accessing the PLBv46 Bridge IPIFBAR_3 with address 0x00000071 on the PLB bus yields 0x876543F1 on the
PCIe bus.
DS540 June 22, 2011
www.xilinx.com
26
Product Specification