DS540 Datasheet, PDF (21/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Bridge Interrupt Register (BIR, Offset 0x40)
The Bridge Interrupt Register shown in Figure 6 is used to send Bridge interrupts to the host processor.
X-Ref Target - Figure 6
Reserved
MSI
MUR MEP
SEP SBO LNKDN
Reserved
0 1 2 3 4 5 6 7 8 9 10 11 12 13
16 17 18
31
SUR MCA SUC SCT SCA NBE
Reserved BME
Figure 6: Bridge Interrupt Register
DS540_06_122309
Table 11: Bridge Interrupt Register Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0
Reserved
Slave Unsupported Request: Asserted when the slave side of the Bridge
1
SUR R/TOW
0b
detects a completion TLP with completion status = supported request from
PCIe.
Master Unsupported Request: Asserted when the master side of the Bridge
2
MUR R/TOW
0b
detects a completion TLP with completion status = unsupported request from
PCIe.
3
MCA R/TOW
0b
Master Completion Abort: Asserted when the master side of the Bridge has
received a timeout from the PLB bus.
4
MEP R/TOW
0b
Master Error Poison: Asserted when the master side of the Bridge has
detected a TLP with the poison bit set from PCIe.
5
SUC R/TOW
0b
Slave Unexpected Completion: Asserted when the slave side of the Bridge
detects an unexpected completion TLP from PCIe.
Message Signaled Interrupt: Asserted when the master side of the bridge
6
MSI
R/TOW
0
has received an MSI MemWr TLP. Implemented only when
C_INCLUDE_RC=1.
7
SCT
R/TOW
0b
Slave Completion Timeout: Asserted when the slave side of the Bridge has
detected a completion timeout
8
SEP
R/TOW
0b
Slave Error Poison: Asserted when the slave side of the Bridge has detected
a TLP with the poison bit set from PCIe.
9
SCA R/TOW
0b
Slave Completion Abort: Asserted when the slave side of the Bridge has
detected a completion TLP with the status = completion abort from PCIe.
10
SBO R/TOW
0b
Slave BAR Overrun: Asserted when the slave side of the Bridge has
detected PLB request with an address outside the BAR address range.
11
NBE R/TOW
0b
Non-Contiguous Byte Enables: Asserted when the slave side of the Bridge
detects a write request from PCIe with non contiguous byte enables.
12
LNKDN R/TOW
Link Down: Asserted when the PCI Express link goes down.
0b
Note: The LNKDN bit is asserted after power up and needs to be cleared by
software.
DS540 June 22, 2011
www.xilinx.com
21
Product Specification