DS125DF1610 Datasheet, PDF (75/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
3. Calculate the second group settings:
Table 21. Manual Data Rate Configuration -- 2^ndGroup Instructions
PARAMETER
Reference Clock
Desired VCO Frequency
Number of Reference Clocks
VCO Freq ÷ 32
Counts of VCO Freq ÷ 32 required
VALUE/EQUATION
F0 = 25e6
F1
N = 1024
F2 = F1 ÷ 32
F3 = F2 x N ÷ F0
Counts of VCO Freq ÷ 32 required rounded F4
PPM error due to rounding
Required PPM tolerance
VCO Freq ÷ 32 +PPM tolerance
Rounded Counts of the VCO Freq ÷ 32
+PPM tolerance required
PPM Counts delta
Err = 1e6 x (F4 – F3) ÷ F3
T
F5 = (1+ T÷1e6) * F2
F6 = F5 x N ÷ F0
F7 = F6 – F3
COMMENT
Internally the reference clock always operates at 25 MHz
F1 is the frequency of the VC0 which is equal to the
desired data rate. If the desired data rate uses dividers, be
sure to multiply the data rate by the divide setting to get
the correct VCO frequency
Round F3 to the nearest integer value. Convert this value
to binary. Program the upper 8 bits to ch register 0x63 and
the lower 8 bits to ch register 0x62. Be sure to set channel
register 0x63[7] to 1 to enable the override function for
manual programming.
Enter the desired PPM tolerance
Round F6 to the nearest integer value
Convert this value to binary. Program the most significant
bit channel register 0x67[6] and the rest of the bits to
channel register 0x64[3:0]
An example for setting group 0 and group 1 to 11.3 Gbps is shown in the Table 22 below.
Table 22. Manual Data Rate Configuration Example
CHANNEL REGISTER (HEX)
0x60
0x61
0x62
0x63
0x64
0x67[7:6]
VALUE
0x80
0xB8
0x80
0xB8
0xEE
2'b00
9 Power Supply Recommendations
9.1 Power Supply Filtering
The power pins on the DS125DF1610 are all internally shorted together on the BGA substrate. This allows board
designers to more easily distribute the bypass capacitors for power supply filtering.
Power supply filtering typically consists of a bulk 22 µF capacitor with an array of 0.1 µF capacitors all placed
near the device. Additional bypass capacitors or capacitors of different values may be required depending on
system conditions. An example array of power supply filtering capacitors is shown in Figure 6.
10 Layout
10.1 Layout Guidelines
The high speed inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 100Ω. Vias should be used sparingly and must be placed symmetrically for each side of a given
differential pair. Whenever differential vias are used the layout must also provide for a low inductance path for
the return currents as well. Route the differential signals away from other signals and noise sources on the
printed circuit board.
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