DS125DF1610 Datasheet, PDF (57/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
75
7:5
4
3
2
1
0
76
7
6
5
4
3
2
1
0
77
7
6
5
4
3
2
1
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Default
Value
(Hex)
0
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
RW
R
EEPROM Field Name
N
RESERVED
N
DFE_POL_5_OBS
0
R
N
DFE_WT5_OBS3
0
R
N
DFE_WT5_OBS2
0
R
N
DFE_WT5_OBS1
0
R
N
DFE_WT5_OBS0
0
RW
Y
POST_LOCK_VEO_THR3
0
RW
Y
POST_LOCK_VEO_THR2
1
RW
Y
POST_LOCK_VEO_THR1
0
RW
Y
POST_LOCK_VEO_THR0
0
RW
Y
POST_LOCK_HEO_THR3
0
RW
Y
POST_LOCK_HEO_THR2
1
RW
Y
POST_LOCK_HEO_THR1
0
RW
Y
POST_LOCK_HEO_THR0
0
RW
N
PRBS_GEN_POL_EN
0
RW
Y
CDR_CAP_DAC_START1[5]
0
RW
Y
CDR_CAP_DAC_START0[5]
1
RW
Y
POST_LOCK_SBTTHR4
1
RW
Y
POST_LOCK_SBTTHR3
0
RW
Y
POST_LOCK_SBTTHR2
1
RW
Y
POST_LOCK_SBTTHR1
0
RW
Y
POST_LOCK_SBTTHR0
Description
Primary observation point for
DFE tap 5 polarity
Primary observation point for
DFE tap 5 weight
VEO threshold after lock is
established. The LSB step
size is 4 counts of VEO.
HEO threshold after lock is
established. The LSB step
size is 4 counts of HEO.
This feature is reserved for
future use. To invert the
polarity of the PRBS data use
the normal method of
inverting of the sign bits for
the FIR taps.
This feature is reserved for
future use
SBT threshold after lock is
established.
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