DS125DF1610 Datasheet, PDF (5/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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DS110DF1610,
DS125DF1610
PIN NAME
TX_2A_P
TX_2A_N
TX_1B_P
TX_1B_N
TX_3A_P
TX_3A_N
TX_2B_P
TX_2B_N
TX_4A_P
TX_4A_N
TX_3B_P
TX_3B_N
TX_4B_P
TX_4B_N
TX_5A_P
TX_5A_N
TX_5B_P
TX_5B_N
TX_6A_P
TX_6A_N
TX_6B_P
TX_6B_N
TX_7A_P
TX_7A_N
TX_7B_P
TX_7B_N
CLOCK PINS
REF_CLK_P
REF_CLK_N
DS150DF1610
PIN NAME
TX_0_3P
TX_0_3N
TX_0_4P
TX_0_4N
TX_0_5P
TX_0_5N
TX_0_6P
TX_0_6N
TX_0_7P
TX_0_7N
TX_1_0P
TX_1_0N
TX_1_1P
TX_1_1N
TX_1_2P
TX_1_2N
TX_1_3P
TX_1_3N
TX_1_4P
TX_1_4N
TX_1_5P
TX_1_5N
TX_1_6P
TX_1_6N
TX_1_7P
TX_1_7N
CLK_MON_P
CLK_MON_N
SMBUS INTERFACE
SDA_IO
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
C2
O, CML Inverting and non-inverting CML-compatible differential
D2
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
C4
O, CML Inverting and non-inverting CML-compatible differential
D4
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
E1
O, CML Inverting and non-inverting CML-compatible differential
F1
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
E3
O, CML Inverting and non-inverting CML-compatible differential
F3
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
G2
O, CML Inverting and non-inverting CML-compatible differential
H2
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
G4
O, CML Inverting and non-inverting CML-compatible differential
H4
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
J1
O, CML Inverting and non-inverting CML-compatible differential
K1
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
J3
O, CML Inverting and non-inverting CML-compatible differential
K3
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
L2
O, CML Inverting and non-inverting CML-compatible differential
M2
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
L4
O, CML Inverting and non-inverting CML-compatible differential
M4
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
N1
O, CML Inverting and non-inverting CML-compatible differential
P1
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
N3
O, CML Inverting and non-inverting CML-compatible differential
P3
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
N5
O, CML Inverting and non-inverting CML-compatible differential
P5
outputs. Driver presents an output impedance of 100 ohms
between these outputs when switching.
P7
I, LVDS/ Inverting and non-inverting
P8
LVCMOS CML-compatible differential inputs for 25 MHz, 125 MHz, or
312.5 MHz clock. These differential signals are typically AC
coupled with 1 µF capacitors
When configured for single-ended input operation, apply
LVCMOS ref clock to REF_CLK_P and float REF_CLK_N.
Single-ended signals should be DC coupled.
A7
O, LVDS Inverting and non-inverting
A8
CML-compatible differential outputs to monitor system
differential clock.
When daisy chaining to another retimer the output frequency
should be set to 25 MHz.
M7
I/O,
Data Input / Open Drain Output
Open Drain External pull-up resistor is required, typically in the 2kΩ to 5kΩ
range. Pull-up value should be selected according to system
implementation.
Pin is 3.3 V LVCMOS tolerant.
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