DS125DF1610 Datasheet, PDF (72/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
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Typical Applications (continued)
specified in the datasheet, multiplied by the number of channels allowed to lock at a time by the lock
sequencer. Then add the static power. The lock sequencer defaults to 8 channels allowed to lock at a time.
To ease the peak power draw, the lock sequencer can be set to allow for only 1 channel to lock at a time.
The lock time for each channel is typically very short, so this power calculation should not be used for the
thermal simulations of the PCB.
• Maximum operational power for thermal calculations. For this calculation use the CDR locked power numbers
specified in the datasheet, multiplied by the number of channels that will be active in the device. Then add the
static power. If it is desired to use the Pattern Generator or PRBS checker, add these powers per channel.
Note that a channel's PRBS Checker and Pattern Generator cannot both be active at the same time. So the
total count of active PRBS Checkers and Pattern Generators should not be more than 16 per device.
• Select a reference clock frequency and routing scheme.
• Plan out channel connectivity. Be sure to note any desired cross point routing in the board schematics.
• Ensure that each device has a unique SMBus address if the control bus is shared with other devices or
components.
• Use the IBIS-AMI model for simple channel simulations before PCB layout is complete.
• Compare schematic against the typical connection diagrams in the datasheet, Figure 6 and Figure 7
8.2.3 Typical Application Performance Plots
Figure 8. Typical Transmit Eye Diagram, 10.3125 Gbps
Figure 9. FIR Transmit Equalization Example,
10.3125Gbps
Figure 8 shows a typical output eye diagram for the DS125DF1610 operating at 10.3125 Gbps with the 1V_PP V_OD
settings. All other device settings are left at default.
Figure 9 shows an example of FIR transmit equalization for a DS125DF1610 operating at 10.3125 Gbps. In this
example, the high speed output is configured for 1V_PP V_OD. The FIR filter is then further adjusted such that the
pre cursor tap is set to -5, the main cursor tap is set to +42, and the post cursor tap is set to -10. An 8T pattern is
used to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.
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