DS125DF1610 Datasheet, PDF (24/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
www.ti.com
The lock sequencer is configurable in the share registers. Users can control which channels are allowed to
attempt lock when a signal is present by configuring share registers 0x0F and 0x10. Users can also limit the
number of channels that are allowed to simultaneously attempt to lock by configuring share register 0x05.
7.3.14.2 RESET_IO Pin
The RESET_IO pin in the DS125DF1610 emulates a power on reset (POR). This type of reset re-initializes the
entire device including the SMBus address strap settings and restores both share and channel register defaults.
The RESET_IO pin triggers a reset on the rising edge of the signal. It is not recommended to hold the
RESET_IO terminal at a logic LOW state for an extended period of time. RESET_IO should be held at logic
HIGH during power on. After power on, the RESET_IO terminal should be pulsed low for a minimum of 10 µs to
perform a reset. After power on, the RESET_IO terminal can be held low longer than 10µs, but the device will
only be in a partial reset state for the during this time. Note, reset and partial reset states are not sleep or power
down states.
7.4 Device Functional Modes
7.4.1 SMBus Master Mode
SMBus master mode allows the DS125DF1610 to program itself by reading directly from an external EEPROM.
When using the SMBus master mode, the DS125DF1610 will read directly from specific location in the external
EEPROM. When designing a system for using the external EEPROM, the user needs to follow these specific
guidelines:
• Maximum EEPROM size is 2048 Bytes
• Minimum EEPROM size for a single DS125DF1610 with individual channel configuration is 1417 Bytes (3
base header bytes + 3 address map bytes + 16 x 88 channel register bytes + 3 share register bytes; bytes
are defined to be 8-bits)
• Set ENSMB = VDD through 1kΩ resistor, enable SMBus master mode
• The external EEPROM device address byte must be 0xA0
• The external EEPROM device must support 400kHz operation at 2.5V supply
• Set the SMBus address of the DS125DF1610 by configuring the ADDR0 and ADDR1 terminals.
When loading multiple DS125DF1610 devices from the same EEPROM, use these guidelines to configure the
devices:
• Configure the SMBus addresses for each DS125DF1610 to be sequential. The first device in the sequence
must have an address of 0x30.
• Daisy chain READEN and ALL_DONE from one device to the next device in the sequence so that they do not
compete for the EEPROM at the same time.
• All DS125DF1610 devices sharing the same EEPROM must be configured with the common channel bit set
to 1. With common channel configuration enabled, each DS125DF1610 device will configure all 16 channels
with the same settings.
When loading a single DS125DF1610 from an EEPROM, use these guidelines to configure the device:
• Set the common channel bit to 0 to allow for individual channel configuration. Or set the common channel bit
to 1 to load the same configuration settings to all channels.
• When configuring individual channels, a 2048 Byte EEPROM must be used.
• If there are multiple DS125DF1610 devices on a PCB that require individual channel configuration, then each
device must have its own EEPROM.
7.4.2 SMBus Slave Mode
7.4.2.1 SDA and SDC
In both SMBus master and SMBus slave mode, the DS125DF1610 is configured using the SMBus. The SMBus
consists of two lines, the SDA or serial data line and the SCL or serial clock line. In the DS125DF1610 these pins
are 3.3V tolerant. The SDA and SCL lines are both open-drain. They require a pull-up resistor to a supply
voltage, which may be either 2.5V or 3.3V. A pull-up resistor in the 2kΩ to 5kΩ range will provide reliable SMBus
operation.
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