DS125DF1610 Datasheet, PDF (65/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
90
7
6
5
4
3
2
1
0
91
7
6
5
4
3
2
1
0
92
7:0
93
7:0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Default
Value
(Hex)
0
0
0
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
RW
RW
RW
RW
EEPROM Field Name
Y
K28P5_COMPR_PERIOD3
Y
K28P5_COMPR_PERIOD2
Y
K28P5_COMPR_PERIOD1
Y
K28P5_COMPR_PERIOD0
0
RW
Y
MIN_K28P5_REQD11
0
RW
Y
MIN_K28P5_REQD10
0
RW
Y
MIN_K28P5_REQD9
0
RW
Y
MIN_K28P5_REQD8
0
RW
Y
MIN_K28P5_REQD7
0
RW
Y
MIN_K28P5_REQD6
0
RW
Y
MIN_K28P5_REQD5
0
RW
Y
MIN_K28P5_REQD4
0
RW
Y
MIN_K28P5_REQD3
0
RW
Y
MIN_K28P5_REQD2
0
RW
Y
MIN_K28P5_REQD1
0
RW
Y
MIN_K28P5_REQD0
0
RW
N
RESERVED
0
RW
N
RESERVED
Description
Used when one of these
modes are enabled, k28.5
lock check(channel register
0x79[5]), 64b66b lock
check(channel register
0x36[3]), k28.5 or 64b66b
Interrupt(register 0x36[0])
k28.5_compr_period defines
period within which k28.5 is
expected to be seen.
Also used for expected
frequency of 64B66B
transitions
The number of bits to check
is equal to
2^(min_k28.5_reqd[11:0]) *
32
Enable K28.5 checking with
reg_79[3]
Used when one of these
modes are enabled, k28.5
lock check(channel register
0x79[5]), 64b66b lock
check(channel register
0x36[3]), k28.5 or 64b66b
Interrupt(register 0x36[0])
Channel register 0x90[3:0]
together with channel register
0x91[7:0] defines number of
k28.5+ patterns that need to
be detected in the number of
bits checked(set by channel
register 0x90[7:4]
Also used for expected
frequency of 64B66B
transitions
Enable k28.5 checking with
channel register 0x79[3]
See channel register
0x90[3:0]
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