DS125DF1610 Datasheet, PDF (28/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
www.ti.com
Address
(Hex)
Bits
4
7
6
5
4
3
Default
Value
(Hex)
0
0
0
0
0
2
0
1
0
0
1
5
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
6
7:0
0
7
7:0
0
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
9
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 13. Shared Registers (continued)
Mode
RW
RWSC
RWSC
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
EEPROM
Field Name
Description
N
SEL_REF_CLK_DIG_OUT_AN 1: Selects the divided clock
A
0: Selects the undivided clock
N
RST_SMB_REGS
1: Resets share registers
N
RST_SMB_MAS
1: Resets SMBus Master
controller
N
RESERVED
N
MR_DIS_LOCK_SEQR
1: Disables the lock sequencer
circuit
0: Normal operation, lock
sequencer is enabled
N
RESERVED
N
RESERVED
N
RESERVED
N
RESERVED
N
CRC_EN
1: Slave CRC Trigger
N
RESERVED
N
EEPROM_READ_DONE
This bit is set to 1 when read
from EEPROM is done
N
LIMIT_CONC_LOCKS3
N
LIMIT_CONC_LOCKS2
N
LIMIT_CONC_LOCKS1
Sets max number of channels
that can lock at any given time,
defaults to 8 channels.
N
LIMIT_CONC_LOCKS0
N
RESERVED
N
RESERVED
N
INT_Q1C3
Interrupt from quad 1, ch 3
N
INT_Q1C2
Interrupt from quad 1, ch 2
N
INT_Q1C1
Interrupt from quad 1, ch 1
N
INT_Q1C0
Interrupt from quad 1, ch 0
N
INT_Q0C3
Interrupt from quad 0, ch 3
N
INT_Q0C2
Interrupt from quad 0, ch 2
N
INT_Q0C1
Interrupt from quad 0, ch 1
N
INT_Q0C0
Interrupt from quad 0, ch 0
N
INT_Q3C3
Interrupt from quad 3, ch 3
N
INT_Q3C2
Interrupt from quad 3, ch 2
N
INT_Q3C1
Interrupt from quad 3, ch 1
N
INT_Q3C0
Interrupt from quad 3, ch 0
N
INT_Q2C3
Interrupt from quad 2, ch 3
N
INT_Q2C2
Interrupt from quad 2, ch 2
N
INT_Q2C1
Interrupt from quad 2, ch 1
N
INT_Q2C0
Interrupt from quad 2, ch 0
28
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