DS125DF1610 Datasheet, PDF (37/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
1B
7:2
1
0
1C
7
6
5
4
3
2
1:0
1D
7
6:0
1E
7
6
5
4
3
2
1
0
1F
7:6
5:0
Default
Value
(Hex)
0
1
1
1
0
0
1
0
0
0
0
0
1
1
1
0
1
0
0
1
0x55
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Table 14. Channel Registers, 0 to 1F (continued)
Mode
RW
RW
RW
RW
RW
RW
EEPROM
Field Name
N
RESERVED
Y
CP_EN_CP_PD
Y
CP_EN_CP_FD
Y
EN_IDAC_PD_CP2
Y
EN_IDAC_PD_CP1
Y
EN_IDAC_PD_CP0
RW
Y
EN_IDAC_FD_CP2
RW
Y
EN_IDAC_FD_CP1
RW
Y
EN_IDAC_FD_CP0
RW
N
RESERVED
RW
Y
SBT_EN
RW
N
RESERVED
RW
Y
PFD_SEL_DATA_MUX2
RW
Y
PFD_SEL_DATA_MUX1
RW
Y
PFD_SEL_DATA_MUX0
RW
N
SER_EN
RW
Y
DFE_PD
RW
Y
PFD_PD_PD
RW
Y
PFD_EN_FLD
RW
Y
PFD_EN_FD
RW
Y
RESERVED
RW
Y
RESERVED
Description
1: Normal operation
1: Normal operation
Phase detector charge pump
setting
MSB located in channel register
0x0C[0]
Override bit required for these bits
to take effect
Frequency detector charge pump
setting
MSB located in channel register
0x0C[1]
Override bit required for these bits
to take effect
SBT enable override
0: Normal operation
For these values to take effect,
register 0x09[5] must be set to 1.
000: Raw Data*
001: Retimed Data
100: Pattern Generator
111: Mute
All other values are reserved.
*Note in this mode the FIR filter
will not function. Data is routed
only through the pre cursor tap.
See Functional Description section
for more information.
1: Enables the serializer for
pattern generation
0: Disables the serializer
This bit must be cleared for the
DFE to be functional in any adapt
mode.
0: DFE enabled
1: DFE disabled
PFD phasee detector power down
override
PFD enable FLD override
PFD enable frequency detector
override
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