DS125DF1610 Datasheet, PDF (26/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
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7.5 Programming
7.5.1 Bit Fields in the Register Set
Many of the registers in the DS125DF1610 are divided into bit fields. This allows a single register to serve
multiple purposes, which may be unrelated. Often configuring the DS125DF1610 requires writing a bit field that
makes up only part of a register value while leaving the remainder of the register value unchanged.
The procedure for accomplishing this is to read in the current value of the register to be written, modify only the
desired bits in this value, and write the modified value back to the register. Of course, if the entire register is to
be changed, rather than just a bit field within the register, it is not necessary to read in the current value of the
register first. In all the register configuration procedures described in the following sections, this procedure should
be kept in mind. In some cases, the entire register is to be modified. When only a part of the register is to be
changed, however, the procedure described above should be used.
Most register bits can be read or written to. However, some register bits are constrained to specific interface
instructions. Register bits can have the following interface constraints:
• R - Read only
• RW - Read/Write
• RWSC - Read/Write, self clearing
• W - Write only
7.5.2 Writing to and Reading from the Global/Shared/Channel Registers
Global registers can be accessed from the shared register page and also the channel register pages. There are
three global registers in the DS125DF1610:
1. Register 0xFC
2. Register 0xFD
3. Register 0xFF
Registers 0xFC and 0xFD are used to select the channel registers to be written to. To select a channel write a 1
to its corresponding bit in these global registers. Note more than one channel may be written to by setting
multiple bits in registers 0xFC and 0xFD. However, when performing an SMBus read transaction only one
channel can be selected at a time. If multiple channels are selected when attempting to perform an SMBus read,
the device will return 0x00.
Register 0xFF bit 1 can be used to perform broadcast register writes to all channels. A single channel read-
modify broadcast write type commands can be accomplished by setting register 0xFF to 0x03 and selecting a
single channel in the 0xFC or 0xFD registers. This type of configuration allows for the reading of a single
channel's register information and then writing to all channels with the modified value.
Table 11. Channel Select Global Registers
GLOBAL
REGISTER
0xFD
BIT
DESCRIPTION
7
Channel 15– Quad 3 Channel 3 – Cross Point Ch D
6
Channel 14– Quad 3 Channel 2 – Cross Point Ch C
5
Channel 13– Quad 3 Channel 1 – Cross Point Ch B
4
Channel 12– Quad 3 Channel 0 – Cross Point Ch A
3
Channel 11– Quad 2 Channel 3 – Cross Point Ch D
2
Channel 10– Quad 2 Channel 2 – Cross Point Ch C
1
Channel 9– Quad 2 Channel 1 – Cross Point Ch B
0
Channel 8– Quad 2 Channel 0 – Cross Point Ch A
CDR/TX PIN ASSIGNMENT
TX_7B
TX_7A
TX_6B
TX_6A
TX_5B
TX_5A
TX_4B
TX_4A
26
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