DS125DF1610 Datasheet, PDF (11/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
CONDITIONS
RETIMER JITTER SPECS
PRBS-15 pattern,
J_TJ
Total Output Jitter
measured to 1e-12
10.3125 Gbps
PRBS-15 pattern,
J_RJ
Output Random Jitter
measured to 1e-12
10.3125 Gbps
J_DJ
Output Deterministic Jitter
PRBS-15
10.3125 Gbps
J_PEAK
Jitter Peaking
Data Rate = 9.8 Gbps,
Peaking Frequency =
1 - 3 MHz
Data Rate = 12.5 Gbps
Peaking Frequency =
3 - 8 MHz
BW_PLL
PLL Bandwidth at -3 dB
Data Rate = 9.8 Gbps
Data Rate = 12.5 Gbps
J_TOL
Input Jitter Tolerance
RETIMER TIMING SPECS
Jitter per SFF-8431
Appendix D.11
Combination of D_J P_J and
R_J
t_D
Propagation Delay from
Rx inputs to Tx outputs
No Cross Point
Cross Point enabled
t_SK
Channel To Channel
Skew
RECOMMENDED REFERENCE CLOCK SPECS
REF_f
Input Reference Clock
Frequency
REF_PPM
REF_IDC
REF_ODC
REF_VID
REF_VIH
REF_VIL
Reference Clock PPM
Tolerance
Input Reference Clock
Duty Cycle
Intrinsic Reference Clock
Duty Cycle Distortion
Reference Clock Input
Differential Voltage
Reference Clock Signle-
Ended Input High
Threshold
Reference Clock Single-
Ended Input Low
Threshold
REF_f = 25 MHz⁽²⁾
REF_f = 25 MHz⁽²⁾
Intrinsic Duty Cycle
Distortion of the reference
clock output from the
CLK_MON pins
Differential mode⁽²⁾
Single-ended mode.
Signal DC coupled to
REF_CLK_P,
REF_CLK_N is float
Single-ended mode.
Signal DC coupled to
REF_CLK_P,
REF_CLK_N is float
(2) Parameter is specified by design and not tested at final production
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
MIN
TYP
0.08
3.6
0.03
<1
<1
5
10
>0.7
MAX
UNIT
UI
mUI_RMS
UI
dB
MHz
UI
3UI + 220ps
3UI + 230ps
<80
-100
40%
25
125
312.5
50%
100
60%
±1%
200
1200
1.75
ps
ps
MHz
PPM
mV_PP
V
0.7
V
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