DS125DF1610 Datasheet, PDF (17/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

www.ti.com
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
In a typical point-to-point switching application users must configure the following for each channel:
1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Cross point enable bit (ch reg 0x96)
5. Perform a CDR reset and reset release (ch reg 0x0A)
Note, when using the cross point switch the local and multi-drive buffer should both be enabled regardless of the
desired configuration.
The cross point switch can also be used to replicate data or perform a broadcast function. The options for this
type of configuration include:
• 1:2 – any channel input to any 2 channels output
• 1:3 – any channel input to any 3 channels output
• 1:4 – any channel input to all 4 channels output
When the cross point switch is configured to replicate/broadcast data a master must be assigned during the
cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels
will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there
must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as
slaves. There cannot be more than one master channel in a broadcast network. In a broadcast configuration, the
straight through path connecting the broadcasting input to its own output needs to be enabled and set to have
master control.
In a typical data replication/broadcast application users must configure the following for each channel:
1. Control bus mux setting (ch reg 0x9B)
2. Data path mux setting (ch reg 0x96)
3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)
4. Master/Slave assignment (ch reg 0x96) -- master/slave bit set to master, master function assigned by mux
setting
5. Cross point enable bit (ch reg 0x96)
6. Perform a CDR reset and reset release (ch reg 0x0A)
7.3.5 DFE with VGA
A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects
of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled,
regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only
during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap
polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be
disabled.
The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity
bit.
DFE Parameter
Tap 1 Weight Range
Tap 2-5 Weight Range
Tap Weight Step Size
Polarity
Table 3. DFE Tap Weights
VALUE (mV) (TYP)
0 - 224
0 - 112
7
+ (positive): Signal is attenuated by the tap weight, register bit = 0
- (negative): Signal is boosted by the tap weight, register bit = 1
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: DS125DF1610
Submit Documentation Feedback
17