DS125DF1610 Datasheet, PDF (58/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Address
(Hex)
Bits
78
7
Default
Value
(Hex)
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
R
EEPROM Field Name
N
UNCORR_ERR_INT
6
0
R
N
PRBS_LOCKUP_STATUS
5
0
R
N
SD_STATUS
4
0
R
N
CDR_LOCK_STATUS
3
0
R
N
CDR_LOCK_INT
2
0
R
N
SD_INT
1
0
R
N
EOM_VRANGE_LIMIT_ERROR
0
0
R
N
HEO_VEO_INT
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Description
This feature is reserved for
future use.
This feature is reserved for
future use.
Primary observation point for
signal detect status
Primary observation point for
CDR lock status
Requires that channel
register 0x79[1] be set.
1: Indicates CDR has
achieved lock, lock goes from
LOW to HIGH. This bit is
cleared after reading. This bit
will stay set until it has been
cleared by reading.
Requires that channel
register 0x79[0] be set.
1: Indicates signal detect
status has changed. This will
trigger when signal detect
goes from LOW to HIGH or
HIGH to LOW. This bit is
cleared after reading. This bit
will stay set until it has been
cleared by reading.
This feature is reserved for
future use.
Requires that channel
register 0x36[6] be set.
1: Indicates that HEO/VEO
dropped below the limits set
in channel register 0x76 This
bit is cleared after reading.
This bit will stay set until it
has been cleared by reading.
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