DS125DF1610 Datasheet, PDF (74/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
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The following procedure describes how to calculate and manually program data rates into the DS125DF1610.
1. Select a divider grouping from the Rate/Sub-rate Table and program that value to channel register 0x2F.
When manually programming the data rate into the device, other rate/sub-rate values may be used to allow
for different divider and group combinations. A list of all preprogrammed divider, group combinations is
shown in the Table 19 below.
Table 19. Divider Options
CHANNEL REGISTER
0x2F[7:4] SETTING
FIRST GROUP DIVIDER SETTINGS
0x0
2, 4
0x1
1
0x2
1, 2, 4
0x3
1, 2, 4
0x4
1
0x5
1
0x6
1
0x7
1, 2, 4
0x8
1, 2, 4
0x9
2, 4
0xA
1, 2, 4
0xB
8
0xC
8
0xD
1, 2, 4
0xE
1
0xF
1, 2
2. Calculate the first group settings:
SECOND GROUP DIVIDER SETTINGS
2, 4
1
1, 2, 4
1, 2, 4
1
1
1
1, 2, 4
1, 2, 4
2, 4
1, 2, 4
1
1
1
1
1, 2
Table 20. Manual Data Rate Configuration -- 1^STGroup Instructions
PARAMETER
Reference Clock
Desired VCO Frequency
Number of Reference Clocks
VCO Freq ÷ 32
Counts of VCO Freq ÷ 32 required
VALUE/EQUATION
F0 = 25e6
F1
N = 1024
F2 = F1 ÷ 32
F3 = F2 x N ÷ F0
Counts of VCO Freq ÷ 32 required rounded F4
PPM error due to rounding
Required PPM tolerance
VCO Freq ÷ 32 +PPM tolerance
Rounded Counts of the VCO Freq ÷ 32
+PPM tolerance required
PPM Counts delta
Err = 1e6 x (F4 – F3) ÷ F3
T
F5 = (1+ T÷1e6) * F2
F6 = F5 x N ÷ F0
F7 = F6 – F3
COMMENT
Internally the reference clock always operates at 25 MHz
F1 is the frequency of the VC0 which is equal to the
desired data rate. If the desired data rate uses dividers, be
sure to multiply the data rate by the divide setting to get
the correct VCO frequency
Round F3 to the nearest integer value. Convert this value
to binary. Program the upper 8 bits to ch register 0x61 and
the lower 8 bits to ch register 0x60. Be sure to set channel
register 0x61[7] to 1 to enable the override function for
manual programming.
Enter the desired PPM tolerance
Round F6 to the nearest integer value
Convert this value to binary. Program the most significant
bit channel register 0x67[7] and the rest of the bits to
channel register 0x64[7:4]
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