DS125DF1610 Datasheet, PDF (34/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
www.ti.com
Address
(Hex)
Bits
B
7
6
5
4
3
2
1
0
C
7:4
3
2
1
0
D
7
6
5
4
3
2
1:0
E
7:0
F
7:0
10
7:0
Default
Value
(Hex)
0
1
1
0
1
1
1
1
0
1
0
0
0
1
0
1
1
0
1
0
0x93
0x69
0x3A
Table 14. Channel Registers, 0 to 1F (continued)
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
EEPROM
Field Name
Description
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
N
STATUS_CONTROL
These bits repurpose channel
register 0x02 to report different
status signals
Y
SINGLE_BIT_LIMIT_CHECK_ON 1: Normal operation, device
checks for single bit transitions as
a gate to achieving CDR lock
N
RESERVED
Y
EN_IDAC_FD_CP3
Frequency detector charge pump
setting bit 3 (MSB)
LSB located in channel register
0x1C
Y
EN_IDAC_PD_CP3
Phase detector charge pump
setting bit 3 (MSB)
LSB located in channel register
0x1C
N
DES_PD
1: Deserializer is powered down
0: Deserializer is enabled
N
RESERVED
Y
DRV_SEL_VOD4
Y
DRV_SEL_VOD3
Used in conjunction with 0x2D[2:0]
to control the VOD levels of the
high speed drivers
Y
FIR_RLOAD_MAX
Y
FIR_SEL_NEG_GM
N
RESERVED
N
RESERVED
N
RESERVED
Y
RESERVED
34
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: DS125DF1610