DS125DF1610 Datasheet, PDF (42/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Address
(Hex)
Bits
30
7
Table 15. Channel Registers, 20 to 39 (continued)
Default
Value
(Hex)
0
Mode
RW
EEPROM
Field Name
N
FREEZE_PPM_CNT
6
0
RW
Y
EQ_SEARCH_OV_EN
5
0
RW
N
EN_PATT_INV
4
0
RW
N
RELOAD_PRBS_CHKR
3
0
RW
N
PRBS_EN_DIG_CLK
2
0
RW
N
PRBS_PROGPATT_EN
1
0
RW
N
PRBS_PATTERN_SEL1
0
0
RW
N
PRBS_PATTERN_SEL0
31
7
0
RW
N
PRBS_INT_EN
6
0
RW
Y
ADAPT_MODE1
5
0
RW
Y
ADAPT_MODE0
4
0
RW
Y
EQ_SM_FOM1
3
0
RW
Y
EQ_SM_FOM0
2
0
RW
N
RESERVED
1
0
RW
N
CDR_LOCK_LOSS_INT_EN
0
0
RW
N
SIG_DET_LOSS_INT_EN
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Description
1: Freeze PPM counter to
allow safe read
asynchronously
Enables the EQ search bit to
be force by channel register
0x13[2]
1: Enables automatic pattern
inversion of successive 16-
bit words when using the
user defined pattern
generator option.
Feature is reserved for future
use.
This bit enables the clock to
operate the PRBS generator
and/or the PRBS checker.
Toggling this bit is the
primary method to reset the
PRBS pattern generator and
PRBS checker.
1: Enable a fixed user
defined pattern. Requires
that the pattern generator be
configured properly to be
enabled
Selects the PRBS generator
pattern to output. Requires
that the pattern generator be
configured properly.
00: PRBS-7
01: PRBS-9
10: PRBS-15
11: PRBS-31
1: Enables interrupt for
detection of PRBS errors.
The PRBS checker must be
properly configured for this
feature to work
00: no adaption
01: adapt CTLE only
10: adapt CTLE until optimal,
then DFE, then CTLE again
11: adapt CTLE until
HEO/VEO threshold in reg
0x33 are met, then DFE,
then EQ until optimal
Sets the desired FoM for EQ
adaption
00: not valid
01: SM uses HEO only
10: SM uses VEO only
11: SM uses both HEO and
VEO
1: enables loss of CDR lock
interrupt
1: enable loss of signal
detect interrupt
42
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