DS125DF1610 Datasheet, PDF (43/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
32
7
6
5
4
3
2
1
0
33
7
6
5
4
3
2
1
0
34
7
6
5
4
3
2
1
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Table 15. Channel Registers, 20 to 39 (continued)
Default
Value
(Hex)
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
EEPROM
Field Name
Y
HEO_INT_THRESH3
Y
HEO_INT_THRESH2
Y
HEO_INT_THRESH1
Y
HEO_INT_THRESH0
Y
VEO_INT_THRESH3
Y
VEO_INT_THRESH2
Y
VEO_INT_THRESH1
Y
VEO_INT_THRESH0
Y
HEO_THRESH3
Y
HEO_THRESH2
Y
HEO_THRESH1
Y
HEO_THRESH0
Y
VEO_THRESH3
Y
VEO_THRESH2
Y
VEO_THRESH1
Y
VEO_THRESH0
N
PPM_ERR_RDY
0
RW
Y
LOW_POWER_MODE_DISABLE
1
RW
Y
LOCK_COUNTER1
1
RW
Y
LOCK_COUNTER0
1
RW
Y
DFE_MAX_TAP2_5[3]
1
RW
Y
DFE_MAX_TAP2_5[2]
1
RW
Y
DFE_MAX_TAP2_5[1]
1
RW
Y
DFE_MAX_TAP2_5[0]
Description
These bits set the threshold
for the HEO and VEO
interrupt. Each threshold bit
represents 8 counts of HEO
or VEO.
In adapt mode 3, this register
sets the minimum HEO and
VEO required for CTLE
adaption, before starting
DFE adaption. This can be a
max of 15
1: Indicates that a PPM error
count is read to be read from
channel register 0x3B and
0x3C
By default, all blocks (except
signal detect) power down
after 100ms after signal
detect goes low.
After achieving lock, the
CDR continues to monitor
the lock criteria.If the lock
criteria fail, the lock is
checked for a total of N
number of times before
declaring an out of lock
condition, where N is set by
this the value in these
registers, with a max value
of +3, for a total of 4. If
during the N lock checks,
lock is regained, then the
lock condition is left HI, and
the counter is reset back to
zero.
These 4 bits are used to set
the maximum value by which
DFE taps 2-5 are able to
adapt with each subsequent
adaptation. Same used for
both polarities.
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