DS125DF1610 Datasheet, PDF (70/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
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8.2 Typical Applications
Figure 5 shows a typical implementation for the DS125DF1610 in a back plane application. The DS125DF1610
can also be used for front port applications. The DS125DF1610 supports data rates for CPRI, Infiniband,
Ethernet, Interlaken and other custom data rates.
Figure 6 and Figure 7 show a typical application of the DS125DF1610. In these diagrams, the DS125DF1610 is
configured for SMBus slave mode programming. Power is supplied to the device through a single 2.5 V plane.
The power supply filtering shown in these diagrams may need to be adjusted to accommodate additional system
power noise. The SMBus and LVCMOS signals in this example use 2.5 V logic. A differential reference clock for
the digital block is applied to the device through 1 µF AC-coupling capacitors. In this example, the high speed
signals are connected to the device in groups of four to allow for the system designer to make use of the 4x4
cross point switches. Note that since the device contains AC-coupling capacitors on the high speed receiver
inputs, the signals can be directly connected to the device. The transmitter outputs of this device should connect
to AC-coupling capacitors placed near the receive inputs of the receiving ASIC.
2.5V
C1
C2
C2
C2 C2
C2
C2
C2
Populate as needed to set
desired SMBus address
2.5V
R2
R3
R2
R3
R2
R2
2.5V
R1
R1
VDD
GND
ADDR0
TMS_IO
TDO_IO
TRST_IO
TCK_IO
TDI_IO
DS125DF1610
Power and Control
Pin Connections
INTERR_IO
ADDR1
READ_EN
EN_SMB
ALL_DONE
RESET_IO
SDA_IO
SCL_IO
REF_CLK_P
REF_CLK_N
CLK_MON_P
CLK_MON_N
2.5V
R1
C3
C3
C1 = 22 PF
C2 = 0.1 PF
C3 = 1 PF
R1 = 4.7 k:
R2 = 1 k:
R3 = 1 k: or 20 k:
Figure 6. Typical Connection Diagram: Power and Control Pins
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