DS125DF1610 Datasheet, PDF (64/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Address
(Hex)
Bits
8E
7
Default
Value
(Hex)
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
RW
EEPROM Field Name
N
SD_CAL_RESET_LV
6
0
RW
N
SEL_DIV48_LV
5
0
RW
Y
EN_CLK_LOOPTHRU_LV
4
1
RW
Y
FIR_SEL_EDGE2
3
1
RW
Y
FIR_SEL_EDGE1
2
1
RW
Y
FIR_SEL_EDGE0
1
0
RW
Y
DFE_SEL_GAIN1
0
0
RW
Y
DFE_SEL_GAIN0
8F
7
0
R
N
EQ_BST_TO_ANA7
6
0
R
N
EQ_BST_TO_ANA6
5
0
R
N
EQ_BST_TO_ANA5
4
0
R
N
EQ_BST_TO_ANA4
3
0
R
N
EQ_BST_TO_ANA3
2
0
R
N
EQ_BST_TO_ANA2
1
0
R
N
EQ_BST_TO_ANA1
0
0
R
N
EQ_BST_TO_ANA0
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Description
This feature is reserved for
future use.
Output reference clock
selection
1: Selects reference clock
from in channel digital
0: Selects reference clock
from adjacent channel output
1: Enable the reference clock
loop through mux
Edge rate (slew rate) control
VGA gain control
Primary observation point for
the EQ boost setting.
64
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