DS125DF1610 Datasheet, PDF (32/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Address
(Hex)
Bits
0
7
Default
Value
(Hex)
0
Table 14. Channel Registers, 0 to 1F
Mode
RW
EEPROM
Field Name
N
CLK_CORE_DIS
6:4
0
RW
N
RESERVED
3
0
RW
N
RST_CORE
2
0
RW
N
RST_REGS
1
0
RW
N
RST_VCO
0
0
RW
N
RST_REFCLK
1
7
0
R
N
SIG_DET
6
0
R
N
POL_INV_DET
5
0
R
N
CDR_LOCK_LOSS_INT
4
0
R
N
PRBS_SEQ_DET3
3
0
R
N
PRBS_SEQ_DET2
2
0
R
N
PRBS_SEQ_DET1
1
0
R
N
PRBS_SEQ_DET0
0
0
R
N
SIG_DET_LOSS_INT
2
7:0
0
R
N
MULTI_PURP_STATUS
3
7
0
RW
Y
EQ_BST0[1]
6
0
RW
Y
EQ_BST0[0]
5
0
RW
Y
EQ_BST1[1]
4
0
RW
Y
EQ_BST1[0]
3
0
RW
Y
EQ_BST2[1]
2
0
RW
Y
EQ_BST2[0]
1
0
RW
Y
EQ_BST3[1]
0
0
RW
Y
EQ_BST3[0]
4
7:4
0
RW
N
RESERVED
3
0
RW
Y
RESERVED
2:0
0x01
RW
N
RESERVED
5
7:0
0x01
RW
N
RESERVED
6
7:0
0x01
RW
N
RESERVED
7
7:0
0x01
RW
N
RESERVED
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Description
1: Disables the primary digital
clock, resets all state machines
0: Normal operation
1: Reset core state machine
0: Normal Operation
1: Resets channel registers,
restores default values
0: Normal Operation
1: Resets PPM counter, EOM
counter, FLD counter, SBT
counter
0: Normal Operation
1: Reset PPM counter
0: Normal Operation
1: Signal is present on high speed
inputs
0: No signal is detected on high
speed inputs
1: PRBS checker detected polarity
inversion 0: No pattern inversion
detected
1: indicates loss of CDR lock after
having acquired it.
Bit clears on read.
1: Indicates if the PRBS-31
sequence is locked
1: Indicates if the PRBS-15
sequence is locked
1: Indicates if the PRBS-9
sequence is locked
1: Indicates if the PRBS-7
sequence is locked
Loss of signal indicator.
Bit is set once signal is acquired
and then lost.
Register configured by setting
channel register 0x0C[7:4]
This register can be used to force
an EQ boost setting if used in
conjuntion with channel register
0x2D[3]
32
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