DS125DF1610 Datasheet, PDF (6/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
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DS110DF1610,
DS125DF1610
PIN NAME
SCL_IO
DS150DF1610
PIN NAME
JTAG INTERFACE⁽¹⁾
TMS_IO
TDO_IO
TRST_IO
TCK_IO
TDI_IO
OTHER PINS
RESET_IO
INTERR_IO
ADDR0
ADDR1
READ_EN
ALL_DONE
EN_SMB
POWER
VDD
Pin Functions (continued)
PIN
I/O
DESCRIPTION
L6
I/O,
Clock input/output
Open Drain _{External pull-up resistor is required, typically in the 2kΩ to 5kΩ}
range. Pull-up value should be selected according to system
implementation.
Pin is 3.3 V LVCMOS tolerant
EEPROM configuration (SMBus Master mode)
B7
I, LVCMOS JTAG Test Mode Select, internal pull-up
C7
O, LVCMOS JTAG Test Data Out
C8
I, LVCMOS JTAG Test Reset, internal pull-up
D6
I, LVCMOS JTAG Test clock, internal pull-up
D7
I, LVCMOS JTAG Test Data Input, internal pull-up
L8
I, LVCMOS Resets registers and state machines on rising edge. Pulse
LOW for minimum of 10µs to perform reset. Pin should be
pulled HIGH during power on.
M8
O, Open Active Low interrupt signal. Pin goes low when an interrupt
Drain
event occurs. Interrupts must be enabled via SMBus.
B6
I, LVCMOS 4 level input strap pin for SMBus address code LSB. Standard
LVCMOS output.
D5
I, LVCMOS 4 level input strap pin for SMBus address code MSB.
Standard LVCMOS output.
G5
I, LVCMOS Tie LOW for SMBus slave mode normal operation. Pin has
internal pull down.
In SMBus slave mode, tie HIGH to force SMBus address =
0x30.
L5
O, LVCMOS EEPROM load status. Pin goes LOW when EEPROM load is
complete.
N8
I, LVCMOS Connect to GND through ≤1kΩ resistor for SMBus slave
operation.
Connect to VDD through ≤1kΩ resistor for EEPROM
configuration
E5, E7, E9,
E10, F5, F6,
F8, F10, G7,
G9, H6, H8,
J5, J7, J9,
J10, K5, K6,
K8, K10
Power VDD = 2.5 V +/- 5%
(1) Refer to the DS125DF1610 Programming Guide for additional information
6
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