DS125DF1610 Datasheet, PDF (35/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
11
7
6
5
4
3
2
1
0
12
7
6
5
4
3
2
1
0
13
7
6
5
4
3
2
1
0
Default
Value
(Hex)
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Table 14. Channel Registers, 0 to 1F (continued)
Mode
RW
RW
EEPROM
Field Name
Y
EOM_SEL_VRANGE1
Y
EOM_SEL_VRANGE1
RW
Y
EOM_PD
RW
N
RESERVED
RW
Y
DFE_TAP2_POL
RW
Y
DFE_TAP3_POL
RW
Y
DFE_TAP4_POL
RW
Y
DFE_TAP5_POL
RW
Y
DFE_TAP1_POL
RW
N
SD_SEL_MUTEZ
RW
Y
DFE_SEL_NEG_GM
RW
Y
DFE_WT1[4]
RW
Y
DFE_WT1[3]
RW
Y
DFE_WT1[2]
RW
Y
DFE_WT1[1]
RW
Y
DFE_WT1[0]
RW
N
RESERVED
RW
N
RESERVED
RW
N
RESERVED
RW
Y
EQ_EN_DC_OFF
RW
Y
RESERVED
RW
Y
EQ_LIMIT_EN
RW
N
RESERVED
RW
N
RESERVED
Description
Manually set the EOM vertical
range, used with channel register
0x2C[6]
00: ±100 mV
01: ±200 mV
10: ±300 mV
11: ±400 mV
1: Normal operation
Bit forces DFE tap 2 polarity
1: Negative, boosts by the
specified tap weight
0: Positive, attenuates by the
specified tap weight
Bit forces DFE tap 3 polarity
1: Negative, boosts by the
specified tap weight
0: Positive, attenuates by the
specified tap weight
Bit forces DFE tap 4 polarity
1: Negative, boosts by the
specified tap weight
0: Positive, attenuates by the
specified tap weight
Bit forces DFE tap 5 polarity
1: Negative, boosts by the
specified tap weight
0: Positive, attenuates by the
specified tap weight
Bit forces DFE tap 1 polarity
1: Negative, boosts by the
specified tap weight
0: Positive, attenuates by the
specified tap weight
Bits force DFE tap 1 weight,
manual DFE operation required to
take effect
1: Normal operation
1: Configures the final stage of the
equalizer to be a limiting stage.
0: Normal operation, final stage of
the equalizer is configured to be a
linear stage.
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