DS125DF1610 Datasheet, PDF (59/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
79
7
6
5
4
3
2
1
0
7A
7
6
5
4
3
2
1
0
7B
7
6
5
4
3
2
1
0
7C
7
6
5
4
3
2
1
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Default
Value
(Hex)
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
R
EEPROM Field Name
N
PWDN_SD
0
R
N
PRBS_CHKR_EN
0
R
N
PRBS_GEN_EN
1
RW
N
PRBS_LCKUP_EXIT_EN
0
R
Y
EN_K285
0
R
Y
CAL_OVERRIDE
0
R
N
CDR_LOCK_INT_EN
0
R
N
SD_INT_EN
0
RW
N
SEL_A7
0
RW
N
SEL_A6
0
RW
N
SEL_A5
0
RW
N
SEL_A4
0
RW
N
SEL_A3
0
RW
N
SEL_A2
0
RW
N
SEL_A1
0
RW
N
SEL_A0
0
RW
N
SEL_D7
0
RW
N
SEL_D6
0
RW
N
SEL_D5
0
RW
N
SEL_D4
0
RW
N
SEL_D3
0
RW
N
SEL_D2
0
RW
N
SEL_D1
0
RW
N
SEL_D0
0
W
N
PRBS_FIXED7
0
W
N
PRBS_FIXED6
0
W
N
PRBS_FIXED5
0
W
N
PRBS_FIXED4
0
W
N
PRBS_FIXED3
0
W
N
PRBS_FIXED2
0
W
N
PRBS_FIXED1
0
W
N
PRBS_FIXED0
Description
This feature is reserved for
future use.
1: Enable the PRBS checker.
0: Disable the PRBS checker
1: Enable the pattern
generator
0: Disable the pattern
generator
This feature is reserved for
future use.
1: Enables K28.5 checking as
a requirement for lock
0: Normal operation
This feature is reserved for
future use.
1: Enable CDR lock interrupt,
observable in channel
register 0x78[3]
0: Disable CDR lock interrupt
1: Enable signal detect
interrupt, observable in
channel register 0x78[3]
0: Disable signal detect
interrupt
This feature is reserved for
future use.
This feature is reserved for
future use.
Pattern generator user
defined pattern LSB. MSB
located at channel register
0x97.
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