DS125DF1610 Datasheet, PDF (18/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
www.ti.com
The VGA is located within the DFE block. The VGA has 2-bit control and allows for 3 levels of boost. The VGA
can be used to assist in the recovery of extremely small signals. Note that the default VGA should be used for
most applications.
Table 4. VGA Boost Settings
VGA BOOST Setting (CH REG 0x8E[1:0])
00 (default)
01
10
11
BOOST (dB) (TYP)
0
6
6
12
7.3.6 Clock and Data Recovery
The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output
Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling
position is fixed at the 0.5UI location for each bit.
By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output
to the FIR filter and differential driver. Users can configure the CDR data to route the recovered clock and data to
the PRBS checker. Users also have the option of configuring the output of the CDR to send raw non-retimed
data, or data from the pattern generator.
The CDR requires the following in order to be properly configured:
• Input reference clock with proper reference clock divider setting to run the PPM counter.
• Expected data rates must be programmed into the CDR either through the rate/sub-rate Table 18 or entered
manually with the corrected divider settings.
7.3.7 Reference Clock
The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for
each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed
values in the rate/sub-rate Table 18 or the manually entered data rates.
The reference clock can be set to any of the 3 allowable frequencies independent of the data rate of the high
speed channel. The input reference clock can be single-ended or differential for the 25 MHz or 125 MHz settings.
If the 312.5 MHz setting is used, the input signaling type should be differential. The reference clock can be output
through the CLK_MON pins for observation or daisy chaining the reference clock to the next device. If the
CLK_MON port is used for daisy chaining then the output frequency should be set to 25 MHz.
If the reference clock port is configured to operate in single-ended mode, the 2.5V LVCMOS clock signal should
be applied to the REF_CLK_P pin. In this configuration the REF_CLK_N pin should be floated (N/C). In this case
the LVCMOS clock signal should be DC coupled into the REF_CLK_P pin. If the reference clock port is
configured for differential mode, it is recommended to AC couple the clock signal into the DS125DF1610 device.
Configuring the reference clock frequency is done in share register 0x02[6:5]. Configuring the reference clock
input port for single-ended or differential mode operation is done in share register 0x0B[4]. Enabling or disabling
the CLK_MON port is done in share reg 0x0A[0]. Selecting the CLK_MON outputs to transmit the divided (25
MHz) or undivided (input frequency) clock frequency is done in share register 0x04[7].
INPUT FREQUENCE
25 MHz
125 MHz
312.5 MHz
Table 5. REF_CLK and CLK_MON Configurations
INPUT CONFIGURATION
DEFAULT CLK_MON
FREQUENCY
Single-ended or Differential
Single-ended or Differential
Differential
25 MHz
125 MHz
312.5 MHz
RECOMMENDED CLK_MON
OUTPUT FREQUENCY FOR
DAISY CHAINING
25 MHz
25 MHz
25 MHz
18
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: DS125DF1610