DS125DF1610 Datasheet, PDF (29/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
A
7
Default
Value
(Hex)
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
B
7
0
6
0
5
0
4
0
3:0
0
C
7:3
0
2
0
1
0
0
0
D
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
E
7:2
0
1
0
0
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Table 13. Shared Registers (continued)
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
EEPROM
Field Name
N
SEL_CLK_FROM_DIG
N
SEL_REFCLK_TX_VCM1
N
SEL_REFCLK_TX_VCM0
N
SEL_REFCLK_TX_VOD1
N
SEL_REFCLK_TX_VOD0
N
RESERVED
N
SEL_REFCLK_TX_SCP
Y
DIS_REFCLK_OUT
N
RESERVED
N
REFCLK_DET
N
RESERVED
N
REFCLK_SINGLE_END
N
RESERVED
N
RESERVED
N
SAR_ADC_RST
N
SAR_ADC_EN
N
RESERVED
N
SAR_ADC_OUT7
N
SAR_ADC_OUT6
N
SAR_ADC_OUT5
N
SAR_ADC_OUT4
N
SAR_ADC_OUT3
N
SAR_ADC_OUT2
N
SAR_ADC_OUT1
N
SAR_ADC_OUT0
N
RESERVED
N
SAR_ADC_OUT9
N
SAR_ADC_OUT8
Description
1: selects ref clk from digital to
transmit out
0: selects ref clk from analog
loop chain to transmit out. All
channels’ analog blocks must
have ref clk loop through
enabled to transmit ref clk out
of device
Sets the output common-mode
voltage:
00: 800mV
01: 1000mV
10: 1200mV
11: Tracks VCC, bias at 1.2V
Sets the output differential
peak-to-peak voltage:
00: 400mV
01: 533mV
10: 667mV
11: 800mV
1:disable
0:Ref-clk TX short-circuit
protection
1: Disable REFCLK_OUT (TRI-
STATE)
0: Enable REFCLK_OUT
This bit is set to 1 when refclk
has been detected
1: Reference clock input port
configured as single-ended
input
0: Normal operation, reference
clock input port configured as
differential input
Resets SAR ADC
Enables SAR ADC
10-bit SAR ADC Output[7:0]
10-bit SAR ADC Output[9:8]
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