DS125DF1610 Datasheet, PDF (67/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
96
7
6
5
4
3
2
1
0
97
7
6
5
4
3
2
1
0
98
7:6
5:0
99
7
6
5
4
3
2
1
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Default
Value
(Hex)
0
0
0
Table 17. Channel Registers, 5A to 9B (continued)
Mode
RW
RW
RW
EEPROM Field Name
N
RESERVED
N
RESERVED
Y
XPNT_SLAVE
0
RW
Y
XPNT_EN
0
RW
Y
EQ_BUFFER_EN[1]
1
RW
Y
EQ_BUFFER_EN[0]
0
RW
Y
EQ_DATA_MUX_IN[1]
0
RW
Y
EQ_DATA_MUX_IN[0]
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
RW
0x0C0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
N
PRBS_FIXED15
N
PRBS_FIXED14
N
PRBS_FIXED13
N
PRBS_FIXED12
N
PRBS_FIXED11
N
PRBS_FIXED10
N
PRBS_FIXED9
N
PRBS_FIXED8
N
RESERVED
Y
RESERVED
Y
DIVSEL_START1_OV
Y
DIVSEL_STOP1_OV
Y
DIVSEL_START2
Y
DIVSEL_START1
Y
DIVSEL_START0
Y
DIVSEL_STOP2
Y
DIVSEL_STOP1
Y
DIVSEL_STOP0
Description
Always configure this bit to be
master. Master control is
assigned by mux selection
1: Channel is a slave
0: Channel is a master
(recommended)
1: Cross Point is enabled
0: Cross Point is disabled
Enable EQ output buffers:
00: Neither buffer in ON (not
recommended)
01: Only local buffer is ON
10: Only multi-drive buffer is
ON
11: Both buffers are ON
Select EQ data and signal
detect bus from one channel:
00: channel A
01: Channel B
10: Channel C
11: Channel D
Channel A = 0,4,8,12
Channel B = 1,5,9,13
Channel C = 2,6,10,14
Channel D = 3,7,11,15
Pattern generator user
defined pattern MSB. LSB
located at channel register
0x7C.
This feature is reserved for
future use.
This feature is reserved for
future use.
This feature is reserved for
future use.
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