DS125DF1610 Datasheet, PDF (33/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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Address
(Hex)
Bits
8
7
6
5
4
3
2
1
0
9
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
Default
Value
(Hex)
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Table 14. Channel Registers, 0 to 1F (continued)
Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
EEPROM
Field Name
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
RESERVED
Y
DIVSEL_VCO_CAP_OV
Y
SET_CP_LVL_LPF_OV
Y
BYPASS_PFD_OV
RW
Y
EN_FD_PD_VCO_PDIQ_OV
RW
Y
EN_PD_CP_OV
RW
Y
DIVSEL_OV
RW
Y
EN_FLD_OV
RW
Y
PFD_LOCK_
MODE_SM
RW
Y
SBT_EN
RW
Y
EN_IDAC_PD_CP_OV
EN_IDAC_FD_CP_OV
RW
Y
DAC_LPF_HIGH_
PHASE_OV
DAC_LPF_LOW_
PHASE_OV
RW
Y
EN150_LPF_OV
RW
N
CDR_RESET_OV
RW
N
CDR_RESET_SM
RW
N
CDR_LOCK_OV
RW
N
CDR_LOCK
Description
Enable bit to override cap_cnt with
value in register 0x0B[4:0]
Enable bit to override lpf_dac_val
with value in register 0x1F[4:0]
Enable bit to override
sel_retimed_loopthru and
sel_raw_loopthru with values in
reg 0x1E[7:5]
Enable bit to override en_fd,
pd_pd, pd_vco, pd_pdiq with reg
0x1E[0], reg 0x1E[2], reg 0x1C[0],
reg 0x1C[1]
Enable bit to override pd_fd_cp
and pd_pd_cp with value in reg
0x1B[1:0]
Enable bit to override divsel with
value in reg 0x18[6:4]
1: Override enable
0: Normal operation
Enable to override pd_fld with
value in reg 0x1E[1]
Enable FD in lock state
Enable bit to override sbt_en with
value in reg 0x1D[7]
Enable bit to overridephase
detector charge pump settings
with reg 0x1C[7:5]
Enable bit to override frequency
detector charge pump settings
with reg 0x1C[4:2]
Enable bit to override loop filter
comparator trip voltage with reg
0x16[7:0]
Enable bit to override en150_lpf
with value in reg 0x1F[6]
Enable bit to override CDR reset
with reg 0x0A[2]
1: CDR is put into reset
0: normal CDR operation
Enable CDR lock signal override
with reg 0x0A[0]
CDR lock signal override bit
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