DS125DF1610 Datasheet, PDF (23/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

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DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
To perform a full eye capture with the EOM, follow these steps within the desired channel register set:
STEP
1
2
3
4
5
6
7
Table 9. Eye Opening Monitor Full Eye Capture Instructions
REGISTER
[bits]
0x67[5]
0x2C[6]
0x11[7:6]
0x11[5]
0x24[7]
0x24[0]
0x25
0x26
0x25
0x26
0x67[5]
0x2C[6]
0x11[5]
0x24[7,1]
VALUE
0
0
2'b--
0
1
1
1
1
1
0
DESCRIPTION
Disable lock EOM lock monitoring
Set the desired EOM vertical range
Power on the EOM
Enable fast EOM
Begin read out of the 64 x 64 array, discard first 4 words
Ch reg 0x24[0] is self clearing.
0x25 is the MSB of the 16-bit word
0x26 is the LSB of the 16-bit word
Continue reading information until the 64 x 64 array is complete.
Return the EOM to its original state. Undo steps 1-4
7.3.13 Interrupt Signals
The DS125DF1610 can be configured to report different events as interrupt signals. These interrupt signals do
not impact the operation of the device, but merely report that the selected event has occurred. The interrupt bits
in the register sets are all sticky bits. This means that when an event triggers an interrupt the status bit for that
interrupt is set to logic HIGH. This interrupt status bit will remain at logic HIGH until the bit has been read. Once
the bit has been read it will be automatically cleared, which allows for new interrupts to be detected. The
DS125DF1610 will report the occurrence of an interrupt through the INTERR_IO pin. The INTERR_IO pin is an
open drain output that will pull the line low when an interrupt signal is triggered.
Note that all available interrupts are disabled by default. Users must activate the various interrupts before they
can be used.
The interrupts available in the DS125DF1610 are:
• CDR loss of lock
• CDR locked
• Signal detect loss
• Signal detected
• PRBS pattern checker bit error detected
• HEO/VEO threshold violation
When an interrupt occurs, share register 0x08 and 0x09 report which channel generated the interrupt request.
Users can then select the channel(s) that generated the interrupt request and service the interrupt by reading the
appropriate interrupt status bits in the corresponding channel registers.
7.3.14 Other Features
7.3.14.1 Lock Sequencer
A channel will temporarily consume a higher amount of power while its CDR is attempting to lock, compared to
when the CDR is locked. In order to reduce the impact of a power consumption spike when data is transmitted to
a DS125DF1610, the internal lock sequencer will limit the number of active channels that are simultaneously
allowed to attempt to lock.
The lock sequencer grants tokens to various channels that have detected a signal at the input to the CTLE. Once
a channel has achieved CDR lock, it returns its token to the lock sequencer. The lock sequencer will distribute
any available tokens on a first come first serve basis to any channel that is allowed to attempt lock and that has
detected a valid signal.
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