DS125DF1610 Datasheet, PDF (14/81 Pages) Texas Instruments – 9.8 to 12.5 Gbps 16-Channel Retimer

DS125DF1610
SNLS482A – APRIL 2014 – REVISED DECEMBER 2015
Functional Block Diagram (continued)
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IN+
IN-
100:
REFCLK_IN
SMBus
2.5V
EQ Cross Point
VGA/DFE
Retimer/CDR
Signal
Detect
Digital Core
Eye
Opening
Monitor
VCO
1.2V
Regulator
2V
Regulator
PRBS
Check
Patt.
Gen
FIR Filter
Driver
100
Figure 2. DS125DF1610 Simplified Data Path Diagram
OUT+
OUT-
7.3 Feature Description
7.3.1 Device Data Path Operation
The DS125DF1610 data path consists of several key blocks as shown in Figure 2. These key circuits are:
• AC-coupled Receiver with Signal Detect
• CTLE
• Cross Point Switch
• DFE with VGA
• CDR
• Differential Driver with FIR Filter
7.3.2 AC-Coupled Receiver with Signal Detect
The differential receiver for each DS125DF1610 channel contains on chip AC coupling capacitors. The minimum
bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.
The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high
speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to
automatically power on or off the rest of the high speed data path depending on if a signal is present. The signal
detect block can be manually controlled in the SMBus channel registers. This can be useful if it is desired
manually force channels to be disabled. For information on how to manually operate the signal detect circuit
please see the DS125DF1610 Programming Guide and channel register 0x14 information.
7.3.3 CTLE
The CTLE in the DS125DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting
stage. The CTLE adapts according to a Figure of Merit (FOM) calculation during the lock acquisition process.
Once the CDR has locked and the CTLE has been adapted, the CTLE boost level will be frozen until a manual
re-adapt command is issued or until the CDR re-enters the lock acquisition state. The CTLE is typically re-
adapted by resetting the CDR, set and then clear channel register 0x0A[3:2].
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